FPGA FlexRIO SCTL LabVIEW 2013 Compilation Problems

[davidpcl]

Hi,

I have an FPGA FlexRIO (7962R) VI that interfaces to a 6585 LVDS board that consists of a SCTL running at 200MHz and using a Xilinx Coregen FIFO.

In LabVIEW 2012 using Xilinx 13.4 I have had no problems compiling this at 200Mhz, but in LabVIEW 2013 using Xilinx 14.4 I am unable to get it to compile reliably about about 170MHz with absolutely no modifications to the code.

The Xilinx FIFO is probably irrelevant as I have tried cloning the VI and removing the FIFO and still get the same problem.

Any ideas, things to try or solutions? 

Thanks,

Dave

[Al.C]

Hi Dave,

Have you tried optimising the Xilinx compiler for Timing?

The link below describes how to access the optimization settings, then select 'Timing' from the design strategy drop-down.

http://digital.ni.com/public.nsf/allkb/EE940C191DDCE9CE86256E5500783A4D

[David-A]

---

Have you tried optimising the Xilinx compiler for Timing?

---

You can't modify the Xilinx compile options of a FlexRIO target.

---

In LabVIEW 2012 using Xilinx 13.4 I have had no problems compiling this at 200Mhz, but in LabVIEW 2013 using Xilinx 14.4 I am unable to get it to compile reliably about about 170MHz with absolutely no modifications to the code.

---

What compile error are you getting? Does not reliably mean that sometimes it does compile correctly? Can you upload a simple example of a piece of code that works in 2012 but not 2013?