FPGA DRAM Invalid Addresses

[PeterFoerster]

Hi all,

we've been having some issues with our FlexRIO 7972R, specifically its DRAM. What we're trying to do is to stream samples to the FlexRIO, process them there and get them back in case there's something wrong with the signal. To achieve this we're storing data in the DRAM which is initialized as Int16[32].

In the first implementation, we allocated the whole 2 GB but only addressed 10M lines. With this configuration we noticed that our samples sometimes disappeared from memory between 0 and 130072. We couldn't find any explanation to this. Is this part of the DRAM used for any other process?

For the second implementation we plan to configure the DRAM to 10M lines. How do I address this? Does it simply start at 0? Will the first 130072 lines also be reserved for something else?

Thanks in advance for any help you can provide!

[Terry_ALE]

1. Data should not disappear from DRAM.

2. The memory addresses start at 0 and count up to as many as have been configured.

What do you mean by 10M lines?  Address locations? Bytes?

[PeterFoerster]

Hi Terry,

thanks for your input.

Regarding 1: I think so, too. The reality however, is different. While debugging our system we found out that data actually disappeared from memory. When we streamed a ramp pattern to it and back, it was all zeros. Might have to check if the behaviour is the same with the other FlexRIOs.

By 10M lines I mean adress locations.

[David-A]

Theres an example that ships with FlexRIO 15.1 and later that demonstrates how to use the DRAM with primitives, the Memory IDL, and the DRAM FIFO IDL. You should take a look at that since it demonstrates the different ways to use DRAM on a FlexRIO target and may help you troubleshoot what you are doing.

Example finder: Hardware Input and Output>>FlexRIO>>External Memory>.Getting Started

There's also a memory integrity example at that same example finder directory location you can use to verify every DRAM address can be written to and read from.