FPGA DDS 64 bit phase register

[dthrash]

Hello! 

I am having some trouble updating the code found at the ni link below to use a 64 bit phase register instead of merely 32 bits. I can switch the control value data types to 64 bit, as well as switch the fancy addition-with-wrap vi's to 64 bit. I am uncertain however how I should alter the -5 logic shift.

Thanks in advance!

http://www.ni.com/example/31066/en/

[BobRodge]

Hi dthrash,

Are you still using the 2048 sample reference waveform in your look-up table? If so, I am not sure what the advantage of using 64-bits for this application would be. Are you trying to have more samples in your LUT? Or are you trying to have more resolution in your interpolation?

[dthrash]

Hi Robert,

Thanks for your swift reply. I am still using the 2048 point LUT. My reason for desiring a 64 bit counter is to decrease the frequency noise of the wave form. The noise goes as the frequency of the update loop the DDS is in divided by 2^n, where n is the number of bits in the counter. Frequency stability is very important to my application so updating to n=64 will be great! 

[Intaris]

I don't think a move to 64 bit is going to do what you think it will do.

You need a better LUT if you want to have a better fidelity in your output.  Having a LUT which covers 11 bits (21 being interpolated) with a 32-bit Phase Register will not be really different from a LUT which covers 11 bits (53 being interpolated) with a 64-bit Phase Register.  The quality of your interpolation will not get dramatically better by throwing more bits at it.

---

@dthrash wrote:

Hi Robert,

The noise goes as the frequency of the update loop the DDS is in divided by 2^n, where n is the number of bits in the counter. Frequency stability is very important to my application so updating to n=64 will be great! 

---

You need to shift the weight between LUT and Interpolation more towards the LUT side in order to get much better results.  If your statement means that when the frequency counter is a multiple of 2^n then this would suggest to me that it is the error using a linear interpolation to approximate a non-linear function which is distorting your data, not the phase register precision.  It doesn't get any less linear by adding bits to the phase register.  The noise goes because in the conditions which you (Freq / 2^n) mention there is NO interpolation going on as the counter is working exactly on the 11-bit boundary of your LUT.

PS You can also implement a quarter-wave LUT isntead of a full-wave LUT which will esssentially give you an extra 2 bits in the LUT for "free".  Check to see what hardware you are using and how large the LUT blocks are.  Is the data being stored in BLock RAM for example?  If so, try to utilise as much of the Block RAM unit as possible (Virtex 5 = 36 kb) because once you use one bit of a Block Ram unit, it's all used.  YOu may as well get the benefit from it.

[dthrash]

Hi Intaris!

Thanks for the info. I agree that my noise analysis does not take the interpolation into account. I also agree that increasing the LUT number of points to utilize the full block of RAM already reserved for the process is a good idea.

Why is it that for an 11 bit LUT I shift (-5) bits? How many bits should I shift given a LUT of N bits? Does this number depend on the phase register bit size?

It is my understanding that I can increase the LUT # of points to 8192 (13 bits). I found this number on the same website as I listed earlier. (Perhaps it is different for my PXI-7852R...I am not really sure how to check)

I still would like to update the phase register to 64 bits...could you outline a brief plan to do so?

Thanks!

[Intaris]

The phase value int he example is 16 bits.  Your LUT is 11 bits.  That's where the shift of -5 comes from.  It's essentially putting the uppermost 11 bits in the lowermost 11 bit positions so that the LUT index is correct.

This shift is the difference between your phase register and your LUT size.  16 - 11 = 5 bits to be shifted.  If you move to 64 bit register 64 - 11 = 53 bit shift.

I think before moving the shift register to 64 bit you should try to increase the size of your LUT and alter the code aprpopriately.  Only then think of changing the phase register.  The LUT part will remain mostly unchanged.  Don't change both at once or debugging will be more difficult.

Shane.

[dthrash]

Shane,

Without changing the accumulator, I updated the bits in my LUT to 13. I changed the shift from -5 to -3. The output wave form had the correct center frequency but was very noisy (up to +/- 1 Hz). With the 11 bit LUT the noise was +/- 10 micro Hz. 

I also tried increasing the size of the accumulator up to 64 bits. I did this by changing the "data type" in the "Sine Cycle.vi" from I16 to I32. I also updated all the numeric controls to be U64. I switched the shift from -3 to -51. However, two red dots appear on the inupt of the "sinecycle.vi". Using the help; show context window I see that the "sinecycle.vi" still expects a word 16 bit input. This surprises me because I changed the data type to I32.

Thoughts???

Thanks so much for your input

[Intaris]

Code, image?

[dthrash]

Here is a picture of the code as well as the code itself.

[dan_u · Accepted solution]

When you split a U64 you get two U32. The SubVI expects U16 (you see the coercion dots because of incorrect data types).

I would suggest shifting the U64 by 3 bits, then split to two U32, split the upper again to two U16. Since you shifted by 3 bits the first 3 bits are 0, resulting in a 13 bit address. The lower U16 is for interpolation.