FPGA Compiler too long

[Benoit]

Is there any way to do a FPGA compiler that compile only the new part or VI of a whole project. It so time consuming to wait for the compiler finish is process.

B.

[Wiebe@CARYA]

Put a disable structure around the parts that you don't need. Works like a
charm.

Regards,

Wiebe.

[Benoit]

And if I'm not programming anything it's gona be faster too.

No... I'm talking about a real solution. If you change a little thing in a VI the whole project will be recompiled. What I'm talking about is having a way that the compiler will recompile only the part that is changed and not the whole project.

B.

[Wiebe@CARYA]

That is not possible. The only way to speed things up a little is to use sub
VI's. Even using reentrant sub VI's instead of duplicate code is a bit
faster. Not much though.

Regards,

Wiebe.

[Benoit]

They should implement that in next version of LabView because in VHDL it's possible to do it.

And I already know all little thing to know that take less space and take less time to compile.

B.

[Eric_Cunningham]

Hi Benoit,

Thanks for your feedback.  Are you familiar with our Product Suggestion Center?  This is the best way to get feedback to our Research and Development department concerning what you would like to see in future products.

[Wiebe@CARYA]

As a suggestion about the "Product Suggestion Center", why isn't there a
list of made suggestions?

I've some suggestions, but they are so obvious that someone else probably
have suggested them, so I feel it's a waste of time.

Regards,

Wiebe.

[Eric_Cunningham]

Actually, if you make a product suggestion that has already been made, it helps R&D know how to prioritize it among the many other product suggestions.  I would recommend submitting any product suggestion that you have, even if it likely has already been made.