FPGA Compile Error: Timing Violation

[xkenneth]

All,

I've got an issue here I've been struggling with for a couple days now. I'm trying to implement a very watered down Kalman filter in the FPGA (I wanted it to run faster than I had it running in the RT.) After quite a bit of optimization, I'm still stuck to no avail. This first thing I tried was simply using the filter I had and changing my math to use fixed point instead of floating point. However this was about 20 operations in series (multiplies, adds, subtracts, and one inverse, (( what's the most efficient way to do an inverse in the FPGA? ))) and the FPGA did not like that at all. So I tried to pipeline the operation. Now mind you this isn't a true pipline because new data cannot be introduced to the pipe in each cycle (I need the output of the last cycle before I can introduce new data,) but I was simply trying to split up the math and have the FPGA only do part of it on each iteration of the while loop, because I thought the FPGA would be able to run this filter way faster than I needed to.

Here's the error I'm getting...

Status: Compilation failed due to timing violations.

Click the Investigate Timing Violation button to display the Timing Violation Analysis window.

Device Utilization

---------------------------

Total Slices: 59.0% (12084 out of 20480)

Flip Flops: 28.5% (11692 out of 40960)

Total LUTs: 45.9% (18788 out of 40960)

Block RAMs: 0.0% (0 out of 40)

Timing

---------------------------

MiteClk (Used by non-diagram components): 33.04 MHz (69.24 MHz maximum)

40 MHz Onboard Clock: 40.41 MHz (30.29 MHz maximum)

Actual Xilinx Options

---------------------------

Synthesis Optimization Goal: Speed

Synthesis Optimization Effort: High

Map Overall Effort Level: High

Place and Route Overall Effort Level: High

Start Time: 6/6/2010 10:11:47 PM

End Time: 6/6/2010 10:57:33 PM 

And then when I try to investigate the timing violations the "Timing Violation Investigator???" gives me this!!:

Possible reason(s):

An internal error occurred. Please try again or contact National Instruments.

Details:

Error Code --> -61499

Error Text --> <APPEND>

Additional Information: There is no matching tag in Xilinx twx file

There is no matching tag in Xilinx twx file

Also,

I was able to successfully run the "Timing Violation Investigator" a couple times. The first time it pointed to a multiply operation which i replaced with high throughput math and pipelined. The second time it pointed to "non-diagram components," how am I supposed to fix that?

I've attached the code and the xflow.log! Thanks for your time!

Thanks!

Ken 

[muks]

Error -61499 in LabVIEW FPGA

[xkenneth]

Hey Muks,

Thanks, that helps, however the timing issues still remain.

Regards,

Ken 

[Hueter]

Can you compile a blank VI?

If you can we know something specific about your code is causing the failure.

If you can't we know that something is wrong with your FPGA install and you will need to repair or uninstall/reinstall.

Also a side note.

-Hunter

[xkenneth]

I can compile the VI just fine without my Kalman filter. I just don't understand why I can't fit my Kalman filter into the FPGA.

- Ken 

[charris]

Hello Ken!

I noticed in your "Kalman_Filter_FPGA_Individual_Stages.vi" that there are 6 unwired subVIs on the block diagram above the main loop. It looks like they may be leftover from the development process (there is one for each stage). Does the compile behave any differently if you remove them?

[xkenneth]

Hey,

Wow, thanks for point that out. I had not scrolled up. That's really embarrassing. 😛 However it still fails to meet timing requirements when removed.

Thanks,

Ken 

[charris]

Hey Ken!

If you hit the "Investigate Timing Violation" button and go to the analysis page, it looks like there are a couple of math functions that are taking longer than expected.

If you replace them with high-throughput math equivalents (from the FPGA Math & Analysis palette) and manually configure the inputs and output FXP word/integer lengths, you might be able to get them within the timing requirements.

Let me know if that works!

[charris]

I'm sorry, Ken. I'd forgotten about the issue with your Investigation window. I'll post up the results I got and see what I can find on that error you're seeing.

[charris]

Ken:

I don't have access to a screen shot right now, but the violations were coming from a subtract function and a multiply function in the stage 5 subVI. If you try replacing the math functions with the high-throughput FPGA math functions, you might have some luck in getting the compile to work.

I think the issue was that the normal math functions were taking too long due to the extra logic required to alter the word/integer length at the output of the functions.