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FPGA Compilation Error (Some signals were not properly constrained in the design)

Hi BobblyLP,

 

I believe you received a timing error, when you tried to compile the VI with this while loop in it. You’ll need to optimize this while loop, in order to avoid this error. You should have used the Timing Violation Analysis Window to identify the part of the VI that is causing this violation.

 

Timing Violation Analysis Window

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgadialog/fpga_time_violation_db/

 

The help document that linked below provides strategies for fixing timing violations.

 

Fixing Timing Violations (FPGA Module)

http://zone.ni.com/reference/en-XX/help/371599J-01/lvfpgaconcepts/fpga_fix_timing_violations/

 

I recommend you use the smallest input data types that represent the data accurately and I recommend you remove coercion dots by explicitly converting between data types. These recommendations can also be found at the KnowledgeBase article that I linked below.

 

Why Does My FPGA VI Generate a Timing Violation at Fixed-Point Multiplication Function?

http://digital.ni.com/public.nsf/allkb/7DFF05C8BB1E999786257B2D005B16F0

 

Regards,

Tunde S.
Applications Engineer
National Instruments
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Message 11 of 13
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Thank you for your advices Tunde_S !

 

So the error "Some signals are not properly constrained in the design" can hide a timing error ? I had indeed a Timing Violation error before I began to post on this topic. But I already solved this problem by partly optimizing  the while loop. I will try to minimize the execution's time of this loop again.

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Message 12 of 13
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I reduced the size of the variable and it compiles ! I don't have any problem now, thank you so much ! Smiley Very Happy

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