LabVIEW
FPGA Clock Accuracy
Sure, you can use the chassis clock as a reference to have a better timing reference.
Make sure however that your 1095 chassis has the 25 ppm clock otherwise you will be using a poorer clock as you can see below (extracted from ni.com) :
However, you will have to configure your reference clock in the LabVIEW software using the Flexrio instrument library (If anyone can clarify further the vi's name) .
Otherwise, if you have more stringent clock accuracy requirements, you can always add a synchronization module to your chassis and use it as the timing reference.
@Jacobson-ni wrote:
Building off of mourad's post, for the 7972R you shouldn't have to do anything special to sync the FPGA clock to the chassis.
But that syncing seems to be done through a PLL, not direct clock connection. A PLL will always introduce some jitter, so it might not be possible to get 50 ppm that way.
@mourad_FAKHFAKH wrote:
Sure, you can use the chassis clock as a reference to have a better timing reference.
Make sure however that your 1095 chassis has the 25 ppm clock otherwise you will be using a poorer clock as you can see below (extracted from ni.com) :
However, you will have to configure your reference clock in the LabVIEW software using the Flexrio instrument library (If anyone can clarify further the vi's name) .
Otherwise, if you have more stringent clock accuracy requirements, you can always add a synchronization module to your chassis and use it as the timing reference.
So with the my chassis, I have it synced to an external clock (I have a 10 MHz clock going into it to PLL to via a timing/sync card and ni sync). If my timing source is highly accurate, do the chassis inherit its accuracy? From the commenter after yours, it sounds like it doesn't? Is there any way to quantify the new accuracy?
@bchang32 wrote:
@mourad_FAKHFAKH wrote:
Sure, you can use the chassis clock as a reference to have a better timing reference.
Make sure however that your 1095 chassis has the 25 ppm clock otherwise you will be using a poorer clock as you can see below (extracted from ni.com) :
However, you will have to configure your reference clock in the LabVIEW software using the Flexrio instrument library (If anyone can clarify further the vi's name) .
Otherwise, if you have more stringent clock accuracy requirements, you can always add a synchronization module to your chassis and use it as the timing reference.
So with the my chassis, I have it synced to an external clock (I have a 10 MHz clock going into it to PLL to via a timing/sync card and ni sync). If my timing source is highly accurate, do the chassis inherit its accuracy? From the commenter after yours, it sounds like it doesn't? Is there any way to quantify the new accuracy?
Let's try and disentangle a couple of topics here. Refresher: https://www.ni.com/en-us/support/documentation/supplemental/06/what-clock-error-means-to-your-measur...
1) What clock accuracy is required for your application? This can be increased from stock 7972 by using a high accuracy frequency reference to your chassis 10MHz input, or by introducing an NI timing card. Your clocks in the FPGA must all be derived from that 10 MHz then, and the accuracy should propagate. If you need a 10 MHz clock and you've got a 25ppm oscillator, then that means your clock freq might be between 9.999750MHz to 10.000250MHz but does NOT imply jitter (separate spec for your oscillator).
2) What Jitter is required for your application? The PLLs in the 7-series add a minimum of 50ps of jitter, which is on top of the jitter of your oscillator. Unless you're running your base clock, or a SCTL off of that 10 MHz input, there will be a PLL inserted in-line between your clock source (highly accurate 10 MHz) and your actual logic, and therefore more jitter.
