FPGA CLIP compilation question

[nickstorton]

Hi All,

I'm not sure this is the correct board for this question but couldn't find anywhere else more obvious. I'm working on a project where I need to develop a UI using LV under Windows and also the FPGA based side of the project. The project will be used to evaluate some IP that one of our developers is creating using VHDL which will be incorporated in an ASIC eventually. My plan is to load this IP into the LV FPGA side using a CLIP node, so far so good. A part of this IP will be a 16-bit 80-tap FIR filter running at 40 MHz. If this was coded simply then there will be very long combinatorial delays so that it won't meet timing at 40 MHz. The VHDL designer has said that in order to implement this he would normally recode his VHDL using Synopsys 'Designware' or Cadence 'Chipware' components such as a 3-stage pipelined multiplier and thus meet timing. So my question is this... if either of these components were used in the vhdl would the NI FPGA compiler understand these components and successfully compile the IP into the CLIP or would he need to use the Xilinx Coregen components? Does anyone have any experience in doing this?

Thanks

Nick

[Intaris]

VHDL is VHDL.

If the clip code is delivered in VHDL, then it should be fine.  How the VHDL got created isn't really important.

[nickstorton]

I get what you are saying but in the VHDL I will get from our designer there will just be the code calling the external pipelined component (see example below) which would then get sucked in by the Synopsis or Cadence compiler if they were used. What I don't know is whether the Xilinx compile chain can also call in that external code at compile time because my feeling is it won't know where to get the components VHDL from. Hence my question on the Coregen component. My guess is that the Xilinx tool chain would know where the component was if it was a Coregen component and could fetch the code at compile time from the library. The thing is we don't use Coregen currently so we don't know what the interface definition is.

Example:

component DW02_mult_3_stage

  generic (

    A_width: integer := 8;

    B_width: integer := 8);

  port (

    A: in std_logic_vector(A_width - 1 downto 0);

    B: in std_logic_vector(B_width - 1 downto 0);

    TC: in std_logic;

    CLK: in std_logic;

    PRODUCT: out std_logic_vector(A_width + B_width - 1 downto 0));

end component;

Thanks for the reply

Nick

[Intaris]

The basic question is whether the export creates the external component as a VHDL file or not.  I'm currently understanding it does not, in which case the Xilinx compiler most likely won't be able to use them, but I suppose someone who actually knows about this stuff should chime in and give us some more information.  We currently have a CLIP VHDL file which consisty of several files, each one representing a component. The clue here is that all the components are also provided in VHDL so there's no problem.

Shane.

[nickstorton]

Hi Shane,

You are correct here. The thing is that whilst these components do exist in vhdl they are contained within the IP library of whoevers' component you are using so you don't have access to the specific vhdl code that performs the actual function only the interface definition for the functions IO. I guess, as you suggest, we do need someone from NI who knows the intricacies of this to chime in.

Thanks again,

Nick

[Intaris]

Well I know that NI also has a lot of IP which they pass to the Xilinx Compiler in VHDL but don't want to publish all their hard work (and bugs! ).

In order to achieve this they encrypt the VHDL files, maybe this would be a viable approach.  I don't know where the decryption takes place.  If the Xilinx Compiler does it itself, then maybe your comonents can be exported in this manner.

Shane.

[Dragis]

Like the others mentioned, if the Cadence and other tools don't produce VHDL for these IP cores (which I doubt they do), you need to find out if there is at least a precompiled implementation for the Xilinx toolchain*. If so, then you can add that package to the list of dependencies in the CLIP configuration and you can use the library. There are very few vendors that do this, so the chances are quite high that you will need the hardware designer to somehow use Xilinx IP cores instead of the others to get this to work.

* And by Xilinx toolchain, I mean the exact same version that LabVIEW FPGA is using to compile the design. The pre-compiled libraries for Xilinx typically are not reusable across versions of the tools.