FIR compiler 7.2

[Serg15]

Hi,

I am having issues with the FIR Compiler 7.2 running on PXIe-7976R FlexRIO.  A DDS with a clock frequency of 250MHz and a phase width of 48 bits is generating two 16 bit sinusoids.  A highpass filter with .7 pi cutoff frequency filters the top 16 bits of the DDS output, which corresponds to sine, and a lowpass filter with .1 pi cutoff frequency filters the bottom half of the bits, corresponding to the cosine.  The outputs of the filters are sent to the host computer through a DMA FIFO.  Below are the output of the the computer.  The top graph is the output of the lowpass filter, while the bottom plot is the highpass filter.  Why am I seeing those artifacts on the highpass filter?  If I zoom in on the highpass filter plot, the artifacts look similar to the transient respond of a filter which would be understandable if they were at the beginning of the plot.  Any ideas?  Attached is the project broken into two parts.  The projects is too big to be uploaded in a single zip file.

Thank you,

Serg

[LocalDSP]

Hi,

     Have you verified your input signals (resp. sine an cosine)? For example if you split the 32 bit DDS output into two 16 bit values, have you converted these from U16 to I16 before your filter?

     Also you can verify the functionality of your filters by applying an impulse to their respective inputs instead of your sine-cosine signals. The FIR should simply return the impulse response and an FFT of that signal should show you the expected frequency response(s).

Just some ideas to track down the source of your problem.