FIFO issue in continuous streaming data from host to target FPGA

[tintin_99]

Hi,

in the below code I stream data from host to target using DMA FIFO.

Here are what I have in host and target sides for write FIFO ( write in host and read in target )

On the host side , I write an array of U32 ( size 6003) to the write FIFO and then I start transactions 

 

On the target side my FPGA clock rate is 60MHz . The whole below code is inside a timed loop with frequency of 60MHz. Based on the divider value, the inner case structure  (which calls Read from FIFO) becomes true every n ticks. So if n=10 then the Write FIFO works at        (60Mhz / 10 =6MHz ) . If n=6 then then the FIFO operates at 10MHz.

When n =6 :

The FIFO works fine. I don’t see the FIFO overflow and the number of elements to read is always 1

For n>6

FIFO overflows and I can’t stream the data from host side to target side.

 

Could you please help me with this? How can I avoid the FIFO to overflow 

[nathand]

Your text says that the FIFO is overflowing (has too much data), but you wired the "Read FIFO Overflow" indicator to the FIFO Read Timeout which indicates that there is no data available. It sounds more likely that your "true every n ticks" logic isn't working properly, and that on the host side you are not filling the FIFO fast enough when n > 6.

[tintin_99]

Thanks nathand

The true every n tick logic works otherwaise I should have this issue even for n<6. I also works it in simulation 

When it overflows, I see the number of elemnts to read from the Write DMA FIFO is either 0 or >1 . Even sometimes 79.

I think when the Number of Elements to Read is greater than 1, it means the host side can't fill the FIFO fast enough

and when the the Number of Elements to Read is zero it means target side can't read from FIFO fast enough.    Is it correct?

And then what is the solution. How can I sync write and read together?

[nathand]

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tintin_99 wrote:

When it overflows, I see the number of elemnts to read from the Write DMA FIFO is either 0 or >1 . Even sometimes 79.

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Again, this isn't an overflow, it's an underflow. LabVIEW uses the term "timeout" to refer to an overflow (the FIFO is full and can't handle any more elements) when writing, and to refer to an underflow (the FIFO is empty) when reading. Timeout means that LabVIEW couldn't do the operation (read or write) within the time period allowed. If you're sometimes seeing a number of elements to read >0 after you fail to read an element, most likely the data is moved into the FPGA FIFO buffer between the read and the check for the number of elements to read.

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tintin_99 wrote:

I think when the Number of Elements to Read is greater than 1, it means the host side can't fill the FIFO fast enough

and when the the Number of Elements to Read is zero it means target side can't read from FIFO fast enough.    Is it correct?

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No, this is backwards. When there are zero elements to read, the FIFO is empty, so the host side is not writing fast enough.

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@tintin_99 wrote:

And then what is the solution. How can I sync write and read together?

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Depends on what your goal is. Most likely, the solution here is to ignore the timeout and try again until you get the data. My guess is the data has not all been transferred to the FPGA when you start trying to read it. The way a DMA FIFO works, there are two buffers - one on the host, and one on the FPGA. The host-side buffer is usually much larger. In the background, data is periodically transferred between these two buffers. You don't have control over that transfer, and I've never seen a specification for the delay between putting data in the host-side buffer, and that data becoming available on the FPGA. Do you know if you always get the timeout reading the first element? (My guess is yes.)

What exactly do you need to synchronize? You aren't showing your full code, so I can't tell what you're doing with the data. Personally I would remove the "Start" function and simply loop until you don't get a timeout. As soon as you don't get a timeout on the read, you know data is available and you can proceed.

[tintin_99]

Thanks for the explanation. So , as you mentioned, target fails to read an element because of underflow and then data goes to the buffer so the number of elements to read becomes greater than 1

I removed the Start button and passed true to my VI, so it will start working as soon as the VI run.

I will also ignore time out but how can I loop the read FIFO inside a timed loop? I think looping is not allowed inside a timed loop

[nathand]

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tintin_99 wrote:

I will also ignore time out but how can I loop the read FIFO inside a timed loop? I think looping is not allowed inside a timed loop

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That's correct, you can't put a loop inside a timed loop, but why would you need to do so? Read from the FIFO on each iteration of the timed loop (or use a state machine, and read only in one state, if that's what you want).

[tintin_99]

Is this not what I am doing right now. I read 1 element every n count 

Actually the logic should work in this way. I have to read 1 element every n FPGA clock ticks

If I put the DNA FIFO read outside of the case structure I will completely mess up how the commands should be sent to the my part

[tintin_99]

Can I use local FIFOs inside the FPGA and transfer data from DMA FIFO to the local FIFO?

[nathand]

I can't tell what you're doing now, because your screenshot is hard to read and overly complicated (for example, why check if a value is equal to false?).

You can certainly leave the DMA Read inside a case structure. As I suggested, you can use a state machine. Start in the state that reads from the FIFO. If there's a timeout, immediately return to that state. If you receive a value, go to another state, do your processing, and wait an additional n cycles before returning to the state that reads from the FIFO.

I don't understand what you're asking about local FIFOs. Yes, you can use them to transfer data between loops, but I don't see how that would help you here, since you probably don't want the local FIFO to be huge.

[Bob_Schor]

Dear Tintin,

     As you should be able to see from your conversations with Nathand (one of the Experts around here), there's a lot of uncertainty in what you are doing, making for a lot of relatively unproductive back and forth between the two of you.

     Here's a suggestion that will get you "useful help" a lot quicker.  You need to do two things (and both are equally important) --

1. Post as an attachment the entire VI that you are discussing.  We can't help effectively if we can't see, study, and "play with" the code.
2. Write a clear description of what you are trying to accomplish.  Don't worry about how to do it (we'll give advice on that), but rather on what you want to do.  For example, you seem to be generating a signal from your FPGA device.  You might say something like "I want to generate a complex sinusoidally-modulated signal with a carrier frequency of 10KHz using a D/A channel on an FPGA Digital Output channel, outputting one point every 10 microseconds.  I want to generate this waveform continually for 45 minutes, with the amplitude and frequency variation specifications being input parameters".  [I just made this up -- it might be total nonsense, but I'm trying to convey the information that we need in order to understand what parameters of your task are important, and an idea of the nature of those parameters.]

For myself, I must confess that while I'm pretty sure that you are doing "something wrong", I don't understand well enough just what you want to do to be able to make any suggestions that I think could help.

Bob Schor