Extremely long Vivado compile times

[Intaris]

I'm starting my first few pieces of work with a Kintex 7 FPGa target and have some questions about Vivado compile times.

I wanted to make a simply test VI which utilises a lot of BRAM, LUT, Register and DSP.  I have a lop-level loop with 192 instances of a simple sub-VI (1x BRAM Read / Write, 1x DSP multiply and a few feedback nodes).  Really nothing complicated.  My problem is that just the "Generating Xilinx IP" takes upwards of 6 hours.  It ocmpiled eventually, but a local compile was over 2x as fast as a cloud compile.  Is this representative for other compiles?

I also tried compiling an instance where I had 3x the top-level loop (3x192 isntances of sub.VI and 3x FP controls) - this should put my Register usage at approx. 60% and LUT also. BRAM around 80% and DSP 90%.  Probably won't compile, but whatever. This compiled for 24 hours, didn't get out of the Generating IP stage and then cancelled the compilation ebcause communication with the compile server broke.  I now have two compiles running in Cloud compile blocking two instances of my 5 licenced compiles.  I have no idea how long they will take.  I can't reconnect to them and I can't cancel the compiles.

I'm wary that this might somehow be a taste of things to come.

[MaxJoseph]

My compiles, where I have >95% slice usage, 50% memory usage and <1% DSP usage, take about 4 hours. I have never done compiles where use a lot of the DSP resources, so I cannot comment on whether this is a general issue!

[Intaris]

When I look at the Xilinx Log during compiles, it takes several hours just to instantiate my BRAM.

And that's just creating the Xilinx IP....

[Intaris]

Here are my files.

No external dependencies except for an 80MHz clock used in the top-level VIs.

One VI (FPGA Load test.vi) has a single SCTL set to run at 80MHz with 24x case structure with 8 individual instances of a sub-VI (FPGA BRAM-Shift-DSP test.vi) included.  For each group of 8 sub-VIs there are some FP controls (no removal of code possible).

The other top-level VI (FPGA load test 3x.vi) simply has 3 instances of the SCTL of the first VI.

Can anyone try compiling this on a PXIe-7976R target and let me know how you get on?

[Intaris]

My compile attempts were on LV 2018 32-bit.

I'm trying a compile in LV 2015 SP1 at the moment.  Will know more tomorrow.

[Stephen_B]

I tried compiling both designs (1x and 3x) on an internally maintained compile server (not the Cloud Compile Service). They both succeeded, the 1x version took ~8 hours, and the 3x nearly 24.

For reference, the machine the 1x version compiled on has an i5 3570K with 32GB of RAM, and the 3x version compiled on a i53570K with 24GB of RAM (I believe both machines are overclocked a bit). Also, this compile server is a shared resource, so it's likely the machines were compiling another bitfile at the same time for at least part of the time.

Here are the details for the compiles:

• LV 2018 (64-bit) (Vivado 2017.2 64-bit)
• PXIe-7976R

FPGA load test

Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 43.1% (27404 out of 63550)
Slice Registers: 17.9% (90929 out of 508400)
Slice LUTs: 23.3% (59127 out of 254200)
Block RAMs: 38.7% (308 out of 795)
DSP48s: 24.9% (384 out of 1540)

Timing
---------------------------
80MHz: 80.00 MHz (Met MHz maximum)
200 MHz Clock: 200.00 MHz (Met MHz maximum)
40 MHz Onboard Clock: 40.00 MHz (Met MHz maximum)

Compilation Time
---------------------------
Date submitted: 1/24/2019 1:11 PM
Date results were retrieved: 1/24/2019 9:20 PM
Time waiting in queue: 00:08
Time compiling: 08:08:48
- Generate Xilinx IP: 07:24:16
- Synthesize - Vivado: 11:24
- Optimize Logic: 02:18
- Place: 14:27
- Optimize Timing: 03:14
- Route: 10:25
- Generate Programming File: 02:29

FPGA load test 3x

Compilation completed successfully.

Device Utilization
---------------------------
Total Slices: 68.7% (43661 out of 63550)
Slice Registers: 33.6% (170999 out of 508400)
Slice LUTs: 26.9% (68466 out of 254200)
Block RAMs: 87.0% (692 out of 795)
DSP48s: 74.8% (1152 out of 1540)

Timing
---------------------------
80MHz: 80.00 MHz (Met MHz maximum)
200 MHz Clock: 200.00 MHz (Met MHz maximum)
40 MHz Onboard Clock: 40.00 MHz (Met MHz maximum)

Compilation Time
---------------------------
Date submitted: 1/24/2019 11:26 AM
Date results were retrieved: 1/25/2019 10:51 AM
Time waiting in queue: 00:15
Time compiling: 23:24:19
- Generate Xilinx IP: 21:52:35
- Synthesize - Vivado: 34:01
- Optimize Logic: 04:05
- Place: 21:44
- Optimize Timing: 05:35
- Route: 19:03
- Generate Programming File: 07:00

[Intaris]

Thanks man.  Cloud compiles seem to take more than 2x longer.....

I think we'll be installing some local compüile servers if this is indicative. This makes cloud compile almost useless for us.

[Intaris]

Can I reactivate this thread to ask:

Why do the cloud compiles take so long with Vivado......? The "Generating Xilinx IP" takes WAY too long.

I'm currently in the implementation / testing phase of my project, and the compile times are killing me. Oh how I used to curse the compile times of ISE, but now.... man, those were the good old days...