External triggering by pulse train

[joamat]

Hello to all,

my application is supposed to be the periodical acquisition (1kHz-clock) of 4-byte-packages

at port 0 (digital channnel consisting of 8 lines representing 8 bit) of an PCI-6251 DAQ-card of NI over a time of 18sec.

Each byte should be read in triggered externally by the rising edge of a clock signal (4 clock pulse burst) at the boards PFI0 input . So the external trigger signal has the form of a periodical pulse train consisting of 4 clock pulses, that is repeated every ms (signal shape see in the attachement). The trigger signal levels meet the TTL specifications.

How can I accomplish this? I tried just everything without success, even vi-examples for that and different configurations (sampling rate, etc.). I don`t get read in consistent data, it seems that the board doesn`t react to the trigger in the right manner and that some bytes get skipped so that the results of the subsequent processing of the data leads to false results.

The application worked once at a pulse frequency of 200Hz (see application vi attached). Is it possible that the hardware reaches its limitations at 1kHz?

What are the restrictions to the digital trigger signal (edge, pulse width).

Some further data of the trigger signal (apart from the picture):

Width of each clock pulse is only 250ns, the pulse-to-pulse period (within the train) is 5,85µs, the time period between each pulse train is 1ms. Could this make trouble for the DAQ trigger acquisition?

I can`t allocate the problem distinct to the programming or to the hardware. Is my DAQ board not capable to handle this measurement task?

Thanks in advance for your help,

Joachim.

[Wolfgang_Z.]

Hello Joachim,

The External trigger is working with TTL compatible signals. The definition of a TTL compatible signal is as follows:

0V - 0.8V = logic low
2.2V - 5V = logic high
Minimum Pulse Width = 10ns
Maximum Rise/Fall Time = 50ns

The hardware doesn't reach it limitation at 1kHz.

Here you can find more detailed specifications of the 6251 board:
http://digital.ni.com/manuals.nsf/websearch/F8E75C366A11CABC86257132004E5628

Please note: The Sample Rate (Hz) is the maximum expected rate of the external source. This value don't have any effect to your measurement. (If the value is higher than the max value of the internal clock you are getting an error because than the external clock rate is to fast for the board.)


Regards,
Wolfgang

[hax]

Hi,

I just wanted to append a query to the answer given to this post.

The rise and fall times for the clock pulses I have been sending to the PFI0 connection of my DAQ (AT MIO E10) are of the order of a micro second. This of course is in excess of the 50ns maximum rise time specified in this thread for the TTL specification of the board of the person who originally asked the question, does this also apply to my DAQ card (I just consulted the manual and didn't find an answer).

So:

The Clock pulse is connected to PFI0

The data line is connected to one of the Analog Input Channels

The VI I have been using to make measurments on the falling edges of the clock pulse is "Acquire N Scans - ExtScanClk".

The reason I ask is because the data I record is vaguely similar to what it should be, but still wrong.

Thanks in advance for any help or guidance!