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Error when using multiple clocks in FPGA

Hi all,

 

I've been having an issue in FPGA whereby the tick count is in order of 1000 out of what it should be. Initially, when the code runs only one tick counter, the output seems appropriate, but introducing a second tick counter causes both values to become significantly larger. Can anyone help me? Once the error strikes, I can't seem to do anything to get it to go back to how it should be; I've tried deleting parts of the afflicted (or so I thought) yet nothing happens. The only thing that cured it previously was changing version from LabVIEW 16.0 to 17.0, as it happened originally in version 16.0; now the error has occurred in 17.0 too.

 

Regards,

 

Dan

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1) Post code (or at very least an image)

2) Are you using a SCTL or a standard while loop?

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