Hello
I am working on flex rio along with analog IO adaptor module (5782) .
I made a simple graphic code on fpga vi with single cycled loop running at IO module clock and within it I use my analog input module.
Now when i compiled the vi then and the end of compilation I received the folllowing error:
"
An error was detected in the communication between the host computer and the FPGA target.
If you are using any external clocks, make sure they are connected and within the supported specifications. Also, verify that the rate of any external clocks match the specified clock rates. If you are generating your clocks internally, please contact National Instruments Technical Support.
"
