Dynamic Variable Speed Signal generation with FPGA

[Rajashekar]

Hi,

I want to generate a variable speed signal (sine wave) in closed loop system. The logic works fine if i keep the speed constant in open loop system. Everything works fine if i try to ramp up the speed and stabilize the speed to the ref. speed. After sometime the speed starts fluctuating and stablizes, this repeats intermittently. When i probed the signal externally through oscilloscope, i saw a dc signal in between sine wave which is distorting the speed. The phase continuation of the sine wave is not affected by this dc signal (which i assume a delay creating a dc signal before generating the next sample point). I am attaching the code for the reference. Can some help me to correct the logic if something wrong. 

My requirement is to generate a dynamically variable speed signal through FPGA. The Speed updation rate from RT to FPGA module is 5-10ms.

Note: I have created a lookup table using FPGA Memory blocks for Speed Signal

[nathand]

What do you want to happen when you change the output rate? Can you provide a graph showing how the signal should look? Right now, when you increase the Timer (ticks) value, your code sits in the Check dt state for a bit longer, which will cause the output signal to stay constant. I think that's what you're seeing, but I'm not sure I completely understood your question.

[Rajashekar]

Hi nathand,

I made a lookup table in the Crank Memory block comprising of 180 cycles of sine wave with 9000 sample points. On exceeding the timer (ticks) each sample point from the crank memroy block has to be generated. The address resets to 0 once it crosses 8999. Basically i need to output each sample point from the Crank memory block once each dt (timer) interval.

Attaching the signal pattern for your reference. 

Note: Each sine cycle has 50 sample points, 90th and 180th cycles are missed by extending the 89th and 179th negative sine signals to 0

[nathand]

So, what should happen when you change the Timer (ticks) value? Are you expecting a smooth transition to the new output rate? Right now, when you change that value, you stay at the current output value for the new, longer period of time, until the new Timer (ticks) value has elapsed, then you resume generating the sine wave at the new rate. I assume that's what's leading to your DC value, unless I've misunderstood. If you want to ramp steadily from one rate to the next, you need more complicated logic that slowly increments the Timer (ticks) value.

If I've misunderstood your problem, could you attach an image from the oscilloscope, showing the problem?

[Rajashekar · Accepted solution]

Hi nathand,

I am sorry, there was no issue with FPGA code, it is working fine. It was the Ethernet communication corrupting the speed data while transferring from custom software application to FPGA RT. Suddenly I got a doubt on Ethernet Communication, placed a waveform chart to monitor the speed data read through Ethernet communication. Then I observed that the speed data was reading 0 intermittently which was making the FPGA to generated dc signal, but the Custome code was giving proper speed. 

As I First solution: I added rpm regulator logic for speed data read through Ethernet which will not allow drastic change in the rpm (+/- 5rpm of Previous rpm).

Second Solution: Integrated the custom code and FPGA RT code in the same VI eliminating Ethernet communication which automatically solved the problem.

Custom code loop runs at 10ms and I kept the Ethernet communication loop at 5ms which I suspect the speed data getting corrupted.

Thanks for your time and support