I am looking at http://zone.ni.com/devzone/cda/tut/p/id/5965 but I still have some questions. I think If I had the referenced file "multirateanalogoutput.zip" it might answer my questions. Alternately:
1. how do I create the "FIFO 0" FIFO vs the "DMA Output FIFO 0"
2. Which one or both are created under the FPGA where would the other be created?
3. Do I want FIFO 0, 1...8 or FIFO 0, 1, & 2
4 I thought only 3 FIFO's were possible. Are the FIFO 0 etc which are target only to the FPGA not counted like the DMA Output FIFO's that transfer from the Host to the Target?
Thanks
Judd Hodgson
Judd
