Do front panel controls wired to 2 parallel loops require arbitration in FPGA?

[grad student]

I am wondering if front panel controls or other terminals wired to two different parallel loops constitute a shared resource that requires arbitration and could potentially cause timing jitter for the two loops in Labview FPGA. Also, is there a list anyhwere of operations and/or functions that are simple enough that they generally would operate in one clock cycle or how many simple operations can be completed in one clock cycle. Thanks

[AllanS]

Hello grad student!

LabVIEW FPGA will take care of that behind the scenes so there will be no jitter. There are documents containing functions that cannot be run in a single cycle

Primitives supported in Single Cycle Loop

As far as how many can be run in a single cycle there is no straight answer for that because of how dependant it is on which VIs you use and how you use them. Let me know if there is anything else I can help with. Have a great day!

Allan S.
National Instruments

[grad student]

Thank you for the reply Allan. When you say Labview FPGA takes care of shared front panel controls so that there is no timing jitter, do you mean that no arbitration goes on. Consider this scenario: two digital output lines are updated in parallel inside a single while loop but only one boolean control is wired to both digital output updates. Do the two digital output updates compete for accessing the boolean control value, requiring some form of arbitration?

thanks again

[AllanS]

Hello Grad Student!

This boolean control is not a shared resource so there is no arbitration.  Don't forget when you are programming the FPGA you are essentially programming hardware so you can think of that control in terms of two wires coming out of the same gate.  I hope this helps let me know if you need more information.  Have a great day!!

Allan S.

National Instruments

[grad student]

How does the scenario change when instead of one boolean control being connected to the two digital output updates, now one local variable is connected to the two digital output updates?  Is there a shared resource now, requiring arbitration?  If so, give me some insight into the differences between accessing a value from a local variable as opposed to a control terminal.

[grad student]

And here is another question, somewhat related:  When I compile the FPGA code, the compile summary shows the board clock frequency that I set my board at.  Then in parentheses is another maximum frequency.  I've read in the document "What Information Can I Get From the Compile Report in LabVIEW FPGA?" that this number is a good estimate of the highest clock speed you can set.  But what exactly does this number mean or where is it coming from?  Is the minimum period (1/max freq) telling me how much time is needed (besides waiting) to complete the operations in the FPGA vi?  What I'm trying to get at is does single clock cycle operation play a part in the meaning of this number (minimum period / max freq).  Thanks again.

[AllanS]

Hello Grad Student!

There is no arbitration nessessary this is all taken care of in the translation from LabVIEW  to the FPGA.  Have a great day!

Allan S.

National Instruments

[AllanS]

Hello Grad Student!

That number you are asking about is a maximum speed in which your code could actually be run at.  This number is determined by what is actually going on inside your code at compile time.  I am unaware of the algorithm that actually determines it.  The single cycle loop will execute one iteration in the time of one cycle of the setting of your clock (which is the other number not the maximum number).  Therefore the role of the maximum number in the execution of the single cycle loop is stating the fastest clock rate you could run your single cycle loop at.  Let me know if there is anything I can be more clear about.  Have a great day!

Allan S.

National Instruments