Design a 32bit counter using HDL Interface

[Kalyansuman]

Hi,

I am new to Labview FPGA, and i am trying to explore the HDL interface node in Labview,
i could sucessfully implement an adder and MAC using the same interface,
and tested the same using a File IO.

But the problem araised when i tried implementing a counter code using the HDL Interface,
the values i observed in the display panel and in the File output are not producing any count.,
is there any care to be taken for implementing the above, the same VHDL code is tested for
producing the count using the simulator.Below is the code which i tried to implement

process( clk, reset )
  begin
    if( reset = '1' ) then
       debug_out <= (others=>'0');       
         debug_cnt <= (others=>'0');       
    enable_out <= '0';
    elsif rising_edge(clk) then
         if (ErrorIn(0) = '0') then
              debug_out <= debug_cnt;
               if(debug_cnt = X"000000FF") then
                        debug_cnt <= (others=>'0');
               else
                       debug_cnt <= debug_cnt + X"00000001";
           end if;           
         else
                debug_cnt <= (others=>'1');       
         end if;
   


      if( enable_clr = '1' ) then
        enable_out <= '0';
      elsif( enable_in = '1' ) then
        enable_out <= '1';
      end if;

end if;
end process;

[Ipshita_C]

Hi Kalyansum,

Can you please provide me answers to the following before we go ahead with the problem:

1. By 'display panel' do you mean front panel?

2. Are you sending this counter data to a file and if yes, what kind?

3. By "it works with the simulator" do you mean that with an actual FPGA card it is producing no data in the front panel and file?

Ipshita C.

[Kalyansuman]

Hi Ipshita,

Thanks a lot for your reply,

1. By 'display panel' do you mean front panel?

       Yes! i mean the Display panel means the Numaric Indicator in the front panel.

2. Are you sending this counter data to a file and if yes, what kind?

     Yes! am sending the output data to a file, am wiriting the data to a binary file.

3. By "it works with the simulator" do you mean that with an actual FPGA card it is producing no data in the front panel and file?

     Yes! it works well when i checked with my modelsim simulator, but when using the Labview FPGA  i could not get proper output.

Anyways am attaching the VI project, please go through and let me know,if some problem is there with the design

Thanks & Regards
KalyanSuman.KV

[Ipshita_C]

Hi KalyanSuman,

I looked at your code and what it is missing are signal assignments. You have to wire regout to whatever signals you are trying to ouput. Please have a look at the following link:

http://zone.ni.com/reference/en-XX/help/371599C-01/lvfpgaconcepts/importing_hdl_code/

I would also look at the following link to understand signal assignments better.

http://www.pldworld.com/_hdl/1/www.ireste.fr/fdl/vcl/lesd/les_4.htm

Basically, the best way is to make your signal assignments before the process begins, so you can do it in the 'architecture' section. Hope this helps.

Ipshita C.

[Kalyansuman]

Dear Ipshita,

Thanks for your advice, i did the modification suggested by you,
and i could not find any improvment in the output., and attaching the modified Vi

please find the obtained output in the ../Output/Out.bin
whereas the expected output is incrimental count of 1 from 0x00000000 to FFFFFFFF.
but you can find in the output file that the count is incriments irregularly.

Can i know is there any limitation for the File IO operations on the FPGA VI ,
becouse the outputs are fed to the output file at the FPGA clock i.e., 40Mhz
can the file operation.

Please go through the  workspace and let me know if any modifications needs to be incorporated.

Thanks & Regards
KalyanSuman KV

[Ipshita_C]

Hi KalyanSuman,

Can you please clarify what you mean by 'limitation on file I/O operations for the FPGA VI'?

Ipshita C.

[Kalyansuman]

Dear Ipshita,

Limitations on FILE IO means,
is there any limitation on the data rate that to read and write to the FILE IO.,

Because, When i modified the counter design to run at low speeds i can see the
proper count in the Output file.,

Here am attaching the modified design for your reference.

In this design am generating one more count by name  out_signal,
when ever the reg_delay1 reaches 0x000001F4, the outsignal_cnt increments
and the same is assigned to out_signal and written to a file.

Thanks & Regards
KalyanSuman KV

[Jared_B]

KalyanSuman KV,

I think you are running into this issue because you do not have any handshaking between the two programs.  Currently the host code is running as fast as possible, and the FPGA code is running as fast as possible, but there is nothing synchronizing the two.  You might look into having some case structures to make sure the data is valid and received before generating the next count value.

[Kalyansuman]

Dear Jared Boothe,

Thanks for your reply!
Since i am new to LabView,
It would be of great help if you can provide me any example of that kind,
like handshaking.

But when i tried to read the 2 inputs from a file and
then add them using the same HDL interface,
and write back the same, Here i didnt face any problem.
In above also i didnt use any handshaking

Thanks & Regards
Kalyan Suman KV

[Jared_B]

Kalyan Suman KV,

Please take a look at the two "Synchronization" examples in the NI Example Finder.  These can be found at the following location:

Hardware Input and Output » CompactRIO » FPGA Fundamentals » Host Synchronization » ...

This location provides two options for synchronizing your RT and FPGA.

I think the reason it was working the other way around for you is the FPGA is most likely running faster than your RT - so it was not ever missing data being sent from the RT to the FPGA.  Whereas the other way with the FPGA running possibly faster than the RT, the new data was being received faster than it could be written to file.