DMA Transfer-Multichannel

[Benvalet]

Hi Everyone,

I was wondering what could be possible causes of the changes in channel positions at the host end when I transfer for example 4 channels from the FPGA. I expect the channels to be arranged in the same manner as they were sent from the FPGA but this is not the case. Could someone kindly give me some ideas. See the attached file.

Regards,

Ben

[GerdW]

Hi Opuk,

are you sure your FIFO never runs full? When the FIFO is full you may lose data, resulting in a "position shift"…

[Benvalet]

I monitor the FIFO and it never runs full (My DMA doesnt timeout). That is my concern. Thanks for the response GerdW.

Regards,

Opuk

[GerdW]

Hi Opuk,

you need to provide more information!

Which sample rates do you use on FPGA?

How fast/often do you read the FIFO?

How many elements are remaining in the FIFO?

How do you monitor the FIFO usage level?

Is the wiring correct? (You never know… :D)

Attach full VIs instead of small images. As it involves FPGA and RT you should attach the full project to include all needed resource definitions…

[Jacobson-ni]

To add to GerdW's original question, you should make sure that you are latching the overflow status on the DMA write in the FPGA VI. Otherwise you can very easily miss timeouts. Also make sure that you are always reading a multiple of 4 elements on the RT side.

[Benvalet]

Hi GerdW,

Thank you for your response. I have attached hereby the Host, FGPA codes and the PID subvi as requested. The problem is that, the first channel I feed from the host is X (fast signal) but on the host end, it becomes the last signal. Why could this be?

Thank you.

Best Regards,

Opuk

[Benvalet]

Hi Matt J,

Thanks for your suggestion. I actually read multiples of the 4 elements but I dont quiet understand what you mean by latching the overflow status. Kindly help me to understand.

Best Regards,

Opuk

[crossrulz]

To make things a little simpler, I would make the DMA FIFO hold values of U64.  You can use the Join Number to combine your 4 I16s into a single 64-bit number to shove down the FIFO.  Then you just use Split Number to get your 4 values back on the RT side.  This eliminates some of the mess of making sure you read 4 samples at a time and checking to make sure you actually got your 4 data points for that data point.

[Benvalet]

Hi Crossrulz,

Thank you so much for you response, I appreciate. I have tried using the Join Numbers in FPGA and Split numbers on the RT side but I bet the problem persists.

Best Regards,

Opuk

[T-REX$]

Hey Opuk,

For a description of what is meant by 'Latching' check out bullet point 5 here: http://www.ni.com/white-paper/11406/en/.

5. Program latches into important nodes.

FPGA loops can execute very quickly so it is easy to miss information.  For instance, say you are monitoring a Boolean for when it is asserted. This Boolean value may only be true one iteration out of thousands. With such high loop rates, it is possible to miss the one high event in a list of lows.  By using a latch on the node of interest the user will be alerted that the event of interest has occurred.

 

This snippet will cause a rising-edge value to remain high indefinitely to make sure you're not just missing the incredibly brief timed-out pulse.

Edit: To be clear, this should go on the FPGA side. Instead of 'Value to be latched' you should have the timed out value of your DMA write go to the 'or' block.