DMA FIFO

[pegel2]

Hi,

I am writing 400 elements to a DMA FIFO of the NI7831 FPGA Target,  the DMA FIFO depth was defined in the FPGA FIFO Properties to 127 elements.

The FPGA Target is running in emulation mode.

No DMA read routine at Host side is running.

So, I was waiting for the FIFO Full Flag but it never rise.

Is there a failure in the write routine or do I something wrong ?

Peter

[jdigiova]

The full flag will never be set in emulation mode.  Data is not actually transferred into the DMA FIFO until the DMA engine starts.  The DMA engine starts using the Host VI.  So without a host interface VI to start the DMA engine, data is never going into the DMA FIFO.

Regards,

Joseph D.

National Instruments

[julesjay]

the DMA FIFO must be started before FPGA run , after FPGA run or doesn't care?

tks

Message Edité par julesjay le 10-25-2006 10:35 AM