DMA FIFO switching beteen channels after FPGA sends

[EnrikDS]

Dear comunity,

I am reading 8 AI with the CRIO at high frequency corresponding to 8 sinusoidal waves from resolvers. Also, I am doing some operations in the FPGA and passing to the RT host 2 FIFOs. One is called resolvers with those 8 channels and the other is called speed and accel. which has 12 channels with 4 angular positions, 4 speeds and 4 accelerations in that order. When I read both FIFOs with the host I wait for the FIFO to have enough elements. I also set the timeout of the FPGA to -1 to avoid problems altought I do not know very well what to select. The problem is that when I read with the Host, the channels do not keep the original order which I used for assembling them in the FPGA and also it is possible to appreciate swithings between channels every few seconds so the information is not consistent and robust. It is not possible to use the information if the channels do not stop changing their relative position.

I would appreciate any ideas in solving this and in incrementing the RT frequency because it is going at maximun of 60 Hz, where I was expecting much more.

Thank you very much.

Regards

Enrique

[Intaris]

Maybe you're overflowing your FIFOs and are losing data.  This can lead to the impression that you have "switching" when you actually have data loss due to too slow reading rate on the RT.

Are you configuring your FIFO size on the RT system?  Try increasing the size to two or three times the current value and see if your data loss decreases.  It costs RAM but is a static allocation so it doesn't affect execution speed much.

Shane.

[EnrikDS]

Thanks, I have tried everything, letting the FIFO the default size of 4095 and configuring the size in the HOST, but it seems that the size  does not affect to the swithing and it is still happening.

What exactly happens when I have an overflow? I really do not care to lose data as long as the next group of data it is in the same position than the previous. I mean, if the channels continue matching I do not mind the FPGA overwritting old data for new one.  Thanks

Enrique

[Intaris]

If you don't mind losing data then the only thing which will help is having the FIFO on the RT side a perfect mulitple of the number of items you're putting in.  IF you read 128 elements at a time, set it to a multiple of 128.  That way if you lose data, your data will at least be "in phase" so to speak.

Otherwise you just need to read faster so that you don't lose data.  If your RT simply can't keep up with the FPGA data speeds, then you're going to always lose data.

[EnrikDS]

Dear Intaris,

I have set up the FIFO depth to a multiple of my readings but the switching is still happening. It usaully starts in the right order but after 1 second the column that has to be the first tends to appear the third one. This error seems to be consistent. And then it keeps iself in the third column forever.  I am doing something wrong because it seems not improve by variying the parameters of the FIFOs. Thanks

Regards

Enrique

[Intaris]

What is the number of elements you are reading at a time and how have you configured the FIFO length?

[EnrikDS]

Hi,

attached are two images to explain which parameters I am using to configure the FIFO. We can focus on the speed FIFO:

-Depth confgured to: 120000

-Number of element in a read instruction: 1200

The FIFO can also be configured in the project explorer, in fact I am not sure if the depth parameter configured in the Block Diagram means the same than the parameter

"Requested number of elements" which appears when you double click in the FIFO at the Project Explorer, that value is 4095. Other values are:

-Target to Host

-Data type: FXP (64 bits, 32 bits)

I hope this helps. Thank you very much for your support.

Enrique

[WillD · Accepted solution]

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@EnrikDS wrote:

Hi,

attached are two images to explain which parameters I am using to configure the FIFO. We can focus on the speed FIFO:

-Depth confgured to: 120000

-Number of element in a read instruction: 1200

The FIFO can also be configured in the project explorer, in fact I am not sure if the depth parameter configured in the Block Diagram means the same than the parameter

"Requested number of elements" which appears when you double click in the FIFO at the Project Explorer, that value is 4095. Other values are:

-Target to Host

-Data type: FXP (64 bits, 32 bits)

I hope this helps. Thank you very much for your support.

Enrique

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When you configure the FIFO from the project expolorer you are defining how much FPGA space to use for the FIFO for buffering before the data is duplicated into the RAM FIFO defined by the property node.

Have you tried setting the time out of the FPGA FIFO write to 0, this would be a lossy FIFO.  You can use the FIFO.GetNumberofElementstoWrite to query how much space is in the FIFO and only write when you have 8 and 12 elements free.

[Intaris]

Are you getting timeouts ont he FPGA side?  I see you have an indicator connected there.  Try ORing the value with a shift register initially set to F so that you retain if your FPGA code EVER showed a timeout.

Only when your FPGA code is not timing out when writing to the DMA channel will your program work.  This is the first place to check.

[crossrulz]

Instead of just reading the number of elements you told it, you should be reading a multiple of that number.  So if you had 2400 elements in the FIFO and your number of elements to read was 1200, you should read the full 2400.  This can be done with a simple Quotient and Remainder and a subtraction (# elements in FIFO - remainder of # elements in FIFO / # elements to read).Reading more will help avoid this data loss issue.