DMA FIFO: RT Host reads really fast but still have element remaining

[MindyNg]

Hi All,

I'm reading data from FPGA using DMA FIFO.

In the FPGA side:  100 kHz

In the Host RT side: 1 MHz (I'm reading 10 times faster than the FPGA sending to make sure that I will not miss any data)

I set the timeout = 0 to advoid underflow error.

PROBLEM:

 - Eventhough I'm reading very fast, the element remaining is stil a non-zeros number (vary from around 1 - 12). And because of that, I'm losing data in the next statemachine.

I've attached the screenshot of my Host VI. The indicator: "buffer at wait" ranges from 0-12 when I ran it.

I appreciate any suggestions and ideas on what the problem is and how to solve it.

--Mindy--

-

[MindyNg]

Addition information:

When I ran the HOST RT, the CPU core is also occupied up to 90 -100 % too. Which I think it is not supposed to be.

And I'm pretty sure it was caused because of the DMA FIFO. But I'm not sure why.

Mindy

[crossrulz]

Why are you only reading 1 sample at a time?  You should read more like 10 samples at a time (since the FPGA is 10x faster than the RT).

And since a DMA FIFO is a polling read, you will use 100% CPU while waiting for data.

[Jacobson-ni]

Does this even need to be done on RT? We don't see the rest of your code but what you have here could be easily done on the FPGA. If you need to be reading your inputs element by element and making decisions based on that, it sounds exactly like something that should be done on an FPGA.

It's pretty normal to have your elements remaining fluctuate a bit, as long as it remains relatively low and isn't continuously growing it's not usually a problem.

[dan_u]

You set the RT loop to run at 1 MHz, but does it actually work at that frequency? In my experience a DMA call (read or write) on the RT takes several us. Did you check the actual loop rate of the RT code?

I would also suggest lowering the RT loop rate but reading several elements at once.

[MindyN]

Hi crossrulz,

Thanks for your reply.

"Why are you only reading 1 sample at a time?" ==> Since there is a header check that need to be done to make sure that it is a "good packet" and the header is a few elements. Because if I read more than one element, I have to deal with the vector manipulation. I was just trying to advoid that because I thought I can read faster than the rate it is sending.

And Thanks for the information about the CPU, I didn't know that.

Mindy

[MindyN]

Hi Jacobson,

Thanks for your reply.

"Does this even need to be done on RT? We don't see the rest of your code but what you have here could be easily done on the FPGA. If you need to be reading your inputs element by element and making decisions based on that, it sounds exactly like something that should be done on an FPGA."

==> In my system, the FPGA is ready data from the RS 422 protocol. My task is the received it in the FPGA, and send data to the RT Host and Window host. I need the RT is because there are more than 1 FPGa that I need to use.  This task is to packetized the message.

The rest of my codes in the RT host are just case structure.

The FPGA code is just to send 8 bits  (aka 1  byte) if U8 at a time.

My VI is just to transmitt data from the sensor, store it somewhere (like a shared variable so everyone in the system can use it). I can packet them in the FPGA but when I send it to the RT, it will just be a bit stream, and then I have to compute the header check again.

Do you have better idea to do that?

Thanks Jacobson,

Mindy

[MindyN]

Hi dan,

Thanks for your reply,

"You set the RT loop to run at 1 MHz, but does it actually work at that frequency? In my experience a DMA call (read or write) on the RT takes several us. Did you check the actual loop rate of the RT code?"  ==> IS there a tool in Labview to check the actual loop rate?

"I would also suggest lowering the RT loop rate but reading several elements at once." ==> If I read in more than 1, I will have to deal with the array manipulation to find the header and to store the packet. I mean it is do-able but more complicated. If reading one element at a time didn't work, I will have to read more than one elements at once.

Thanks dan,

Mindy

[dan_u]

The timed loop already provides that information. Expand the "Output Node" on the left inside the timed loop (where you see "Error" now), and you'll get information about the loop iterations (like expected end, actual end, finished late, ...).