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Correct structure for simultaneous input (analog) and output (FPGA)

I'm writing a VI to perform the following experiment. I oscillate a piezo stage in one dimension (x), and while doing that, I read some data from an analog input. Then I move the stage to a new z location, wait for it to settle there, and repeat. I've seen lots of forum topics and example projects about doing Analog Input and Analog Output simultaneously (like in the DAQmx "Synchronization" examples or this forum post). The difference here is that the piezo stage is controlled by an FPGA. So rather than doing a DAQmx Write for the output, I use a Read/Write Control that communicates with the FPGA.

 

My thinking is to have one loop (let's call it the fast loop) continuously oscillate the stage in x, and then use a parallel loop (which can repeat much less frequently, so it's the slow loop) to move the stage to each z location and read data. If I weren't doing this purely in LabVIEW, I would continuously oscillate the x position by simply having a function generator feed a modulation signal to the piezo controller's x channel. Anyway, I attached the VI I made for a first attempt. For the final product, I'd make the fast loop a timed loop (I'm running this on a Real-Time system) rather than a simple while loop with a 1ms wait. I care about this problem because there will be lots of situations when I want to change piezo positions quickly while doing other slower-looping operations. I'm no LabVIEW expert, so I want to make sure I'm not approaching this in a fundamentally misguided way!

 

Here are my questions:

  1. Is the use of the two parallel loops a reasonable structure for my program? Another structure/approach I considered was to have the FPGA vi deal with oscillating the stage (have it continuously calculate and output the stage positions). But then I'd have to compile and deploy different FPGA vi's for different situations. I also considered forcing the Analog Input reads and the stage movements to have the same frequency, so they could both exist in the same loop.
  2. Will the "Wait 10 ms" in the slow loop mess things up? I.e. do the parallel loops have to take turns executing, or can the fast loop be iterating while the slow loop is sitting in its wait?
  3. I'm assuming the slow loop can afford to be slow because data can accumulate on the buffer and then be read all at once. For example, if I have a sampling rate of 1 kHz and I want to read 1000 data points, the read loop will only need to execute once per second (plus the time needed to write the new z location and the wait). Is my understanding on that correct?

In case it's relevant, here are some numbers I might use. Oscillate the stage with a frequency of 5 Hz. Write 100 different positions per cycle, so perform writes at 500 Hz. Might as well read at 500 Hz too, and collect data for 5 oscillations (i.e. one second, 500 samples). It's also worth emphasizing that I don't care about getting the timing synchronized between my reads and my stage movements. I only care about the standard deviation of the Analog Input signal that I read.

 

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Which FPGA card are you using?


Certified LabVIEW Architect, Certified Professional Instructor
ALE Consultants

Introduction to LabVIEW FPGA for RF, Radar, and Electronic Warfare Applications
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A PXI-7841R. It lives in a PXIe-1082 chassis.

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