Compilation failed due to timing violations

[Jale]

Hello!

I am using a PCI 7833R device with a 160 MHz Single Cycle Timed Loop in FPGA VI. Sometimes, the compilation succeeds without any problem, sometimes it does not due to timing violations. The interesting point is that the difference between requested and achieved rate is then usually very very small. (Requested rate 160.52 MHz, achieved rate 160.34 for example). Even if I reduce the clock rate to 80 MHz, the same problem still sometimes occurs (Requested rate 80 MHz, achieved rate 79.99 for example). What is the reason for such a failure? Can I change the compilation strategies? 

Thank you

Jale

[ErnieH]

LabVIEW 2009, they added some options for compiling. You can change the effort to high. May help but will cause longer compile times.

[Jale]

Thanks for answering.

I am using Labview 8.5 and at the FPGA Target Properties Window I can see only the options genaral, top-level clock and conditional disable symbols. Unfortunately, there is no tab with Xilinx options.

[ErnieH]

Don't know how to do this in 8.5. Found a link with the improvements for each module that you may find interesting.

http://www.ni.com/fpga/upgrade.htm

Good Luck.