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Compilation failed due to a Xilinx error

I'm getting a "Compilation failed due to Xilinx error" trying to compile code in LabVIEW 2011.  This code runs on a FlexRIO (PXIe-7962R) with an adapter module (NI 5751).  The issue comes when using the IDELAY clip node to synchronize the start of collection between two flexrio/5751 pairs.  The error message mentions "internal_IDELAY_CLIP_DataOut) has DELAY_SRC set to either I or IO but IDATAIN is not driven by an IBUF".  When we faced this issue before it was solved by following the steps in the following knowledge base article:

 

http://digital.ni.com/public.nsf/allkb/BBD7A87F2ADC2028862577FB005F6B19

 

These patches only mention LabVIEW 2010 but since I'm using LabVIEW 2011 they don't apply.  Any suggestions on what is causing this issue?  I verified that if I remove this clip node it compiles successfully.

Systems Engineering - National Instruments
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Hi Andy,

 

As mentioned in the KB "this issue is caused by a bug in the Xilinx ISE compiler". It is not related to the version of LabVIEW, but it is related to the version of your compiler. Which version of Xilinx compiler are you using? (Check the contents of the C:\NIFPGA\programs folder). If you are still using the 11.5 version then you can still use the patch even if you are running LabVEW 2011.

Sev K.
Senior Systems R&D Engineer | Wireless | CLA
National Instruments
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Hi Sev,

 

I have similar problem, I am using compiler 12.4, however 10.1 is also installed. I  have reinstalled NI Labview FPGA  and the xilinx tools but it did not help. Strangely 7961R VI compiles fine. Previously 7962R was also successfully compiling when I was using Labview 2010.

 

Can you suggest something to me.

 

S G Khan

University of Bristol

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Hi Andy,

 

Did you manage to solve the problem as I have similar problem.

 

Thanks

 

 

S G Khan

University of Bristol

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SG:

 

The ultimate solution was to disable the synchronization regsiters on all the clip inputs.  This is done by right mouse clicking each clip input and going into the property menu.  In the "Advanced Code Generation" section, set the "Number of Synchronizing Registers for Output Data" to 0.

 

Doing this solved my issue and allowed my compile to complete successfully.

 

Andy

Systems Engineering - National Instruments
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Hi Andy,

 

Thanks for this.  I will give it a try, however, in the mean time when I removed the Analogue module (NI 5781)  I could compile my VI on the same FPGA 7962R. I connected the Analogue module NI 5781 to another FPGA Module NI 7961R and get the same xilink error.

 

So its looks like that the Analogue Module is causing compilation error. Any suggestion on this?

 

 

 

Thanks

 

S G Khan

University of Bristol

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SG:

 

This sounds different then my situation.  The clip node that I was including was to synchronize the timing between two 5171's.  If I didn't include the clip node I didn't see the issue (regardless of whether the card was installed or not).

Systems Engineering - National Instruments
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