Communication between the FPGA Master and the 9144 FPGA

[Frans_Wijnen]

Dear all,

I am trying to construct a compact RIO system with one (or possibly more) NI 9144 ethercat modules daisy chained to the the master cRIO system. The 9144 modules is in FPGA mode, with a pretty straight forward digital input to 20 bit integer value conversion (stored in an U32). This U32 data is required on the master FPGA for further processing of the inputs on that system.

My question is this: how to I access that U32 on the 9144 FPGA directly from the master FPGA, i.e. I do not want to transfer it via the RT!

A second question is the following: the 9144 has a digital input on which there will be a rising edge. This is the trigger for the system to convert the digital inputs to the U32, and I would also like to use that rising edge to trigger analog acquisition on the master FPGA. Is that possible?

I would appreciate any help you can offer. Also, I think it would be great to have a whitepaper of some sort available on the first question, as this feature is advertised but not explained.

Cheers!

Frans

[A.E.M]

Hi Frans.

When using the EtherCat expansion chassis, you don't have all the normal options for transferring data that you might be used to from your RIO controller. The only option you have is to use User-Defined I/O Variable. You can read more about that, and how to synchronize I/O in the follow two papers:

Programming EtherCAT I/O With FPGA Intelligence

NI 9144 Expansion Chassis Under the Hood

Since the EtherCat communication is handled by the RT target, you need to pass your data through the RT, in order to be able to pass some data from one FPGA to another FPGA from a different chassis.

If you need highspeed communication between the two FPGA's, you can use a DIO module where you can send trigger information, etc.

[Frans_Wijnen]

Dear Alex,

Thanks for your reply. I am a bit confused now. This page http://www.ni.com/white-paper/7299/en/ describes the ethercat protocol and states that each station reads from the ethercat train, while streaming the ethercat train to the next station. So, each station has access to the data on the ethercat train, therefore I would expect that all FPGAs have access to the ethercat train. So a few more question come to mind:

1. Why would the master controller be different?

2. Are the I/O of the master on the ethercat train?

3. If all NI9144 modules act as described in that white-paper, how do I then access the ethercat train in a second NI9144 to access I/O-data that was placed in the ethercat train by the first NI9144?

Cheers,

Frans

[A.E.M]

Hi Frans.

In theory, the EtherCat protocol does support direct data transfer. Direct data transfer means it can only do from one slave to any subsequent slave. However, the NI Master doesn't allow us to do that... So, to use the train terminology; You can ride the train, but you can't control it. How the data is transferred is a background process that the user can't see or modify.

UDV is required to transfer the data, and thus you need to pass your data by the RT target.

What are you requirements to your application? Are you having any performance issues?

If you really really need a "direct" FPGA-FPGA transfer mechanism, you might want to consider adding a DIO module in each chassis, and then make your own protocol to send data between the chassis.

[Frans_Wijnen]

Hi Alex,

We have two acquisition station located at other ends of our building, so about 20-25 m distance between them as the bird flies, but cable length is probably longer. Also the cable conduits are quite packed, so new cables are not our preferred choice. Hence I am looking for a way to connect both stations, but have the data transferred in a real-time manner. One is reading of high currents (up to 40 kA) and the other station measures voltages over magnet coils. The systems monitors the data and shuts down the current if a resistance deviation is measured over a magnet coil.

I can implement that on the RT of the master, would not really be a problem, but I thought the FPGA would also be a nice place to handle the protection. Then the RT would just take care of some visualisation.

I guess that in my case I should set the FPGA on the master to scan engine - as I only wish to collect data there - and use direct FPGA on my slave to do some processing on the inputs to get the data needed. The RT master then gets my FPGA-computed data and the other data and can do processing on those. Wouldn't you agree?

Cheers,

Frans

[xband]

Hi Alex,

I'm running into the same issues now.  In our application we're using a Ethercat Rio module downstream of a cRIO-9081 running in FPGA realtime mode, not SCAN mode. 

I'm confused about the way these things operate.  The FPGA on the Ethercat does not run independently?  In our perfect world we would program the 9144 FPGA and have it running, communicating back to the main FPGA on the 9081. 

Is this not how these things operate?

Thanks,

Jim

[crossrulz]

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xband wrote:  In our perfect world we would program the 9144 FPGA and have it running, communicating back to the main FPGA on the 9081.

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The EtherCAT does not talk with the cRIO FPGA.  It communicates with the cRIO's RT using the scan engine.  The 9144's FPGA does run independently of the cRIO master.

[xband]

HiCrossrulz,

I have successfully compiled an FPGA vi but when I try to execute the vi the an error appears, "You cannot run this VI because this target does not support interactive execution. Refer to the ....."

I'm running my cRIO-9081 in "LabVIEW FPGA Interface" mode.  I'm hoping to stay in this mode.  I don't see a way to change the EtherCat Modules to this same mode. My Ethercat Shows up as a "master". 

Thanks for your quick response.  I'm not finding a great deal of documentation on the EtherCat . 

Jim

[Frans_Wijnen]

Hi xband,

I am not really sure on the exact why of your question, but I found that you need to compile the FPGA program for the 9144 and once compiled, right-click the target and choose download. The program will then be downloaded to the 9144 and starts running immediately.

My best guess answer to 'why you cannot run the VI on the 9144 in interactive mode' would be that ethercat has insufficient bandwidth to stream all the data needed for interactive mode. I found a document on the NI website warning about the limit amount of data you can transfer in user defined variables (512 bytes or so).

BTW: I use a microsecond timer to create a 1 Hz block wave (on/off) which I then connect to the FPGA LED of the 9144. That's a quick way to see on the hardware that your program is really running. Good luck with your application.

[crossrulz]

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xband wrote:

I'm running my cRIO-9081 in "LabVIEW FPGA Interface" mode.  I'm hoping to stay in this mode.  I don't see a way to change the EtherCat Modules to this same mode. My Ethercat Shows up as a "master".

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You still need to configure the Scan Engine on the cRIO.  Under your EtherCAT Master should be a slave device (the 9144).  That is where your FPGA needs to go.

I also like to flash the FPGA LED so that you can see that the hardware is running.  It is really simple to program and is so useful.