Cannot get data to host from DMA FIFO inside case structure inside single cycle timed loop...

[Idratherberacing]

The program compiles and runs and is able to communicate with the FPGA VI since I can adjust pulse width and period (and I'm confirming via oscilloscope).  The problem lies in the DMA FIFO.  When I leave the timeout at 5000, it times out every time.  I changed it to -1 thinking maybe the transfer rate was really slow.  But, it just hangs here and doesn't do anything.  I'm not quite sure why.

I'm using LabVIEW 8.5 and am running a PXI-7813R device w/ a Windows host.

Attached, please find the code.  Any and all help is appreciated.  Thanks!

[Charlie_P]

Hello Idratherberacing,

You sad the DMA FIFO is timing out.  What, specifically, is timing out? (i.e. Read, Write, FPGA, RT)  How are you changing your pulse width?  Try running your code with Highlight Execution selected so that you can confirm that the code is executing as desired.  Is your FIFO being written to?