04-01-2009 09:45 PM
Can fpga do peak hold like the attached drawing.
The orignal pulse is about 0.3us wide. The wide of the peak hold is 20us.
The peak amplitude is of 0.8V.
Thanks.
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04-01-2009 10:09 PM
04-01-2009 10:31 PM
The fastest cRIO analog input module is the 9201, which samples at 500 kHz, which is equivalent to 2 us intervals. That would not be fast enough to catch your pulse.
The fastest R series board is 750 kHz, which still is not fast enough.
If you built a simple comparator circuit that would convert your pulse to a TTL level signal, you could connect it to a digital input on the FPGA (probably R series only) and read it fast enough. You could use that signal to turn an analog output on and off at the right times. It wouldn't exactly be a peak hold, but it would be pretty close.
Hopefully this gets you closer to an answer to your question.
Bruce