CRIO Fpga program time delay problem!!!

[Sea1]

Hello everyone;

I have a problem in labview program to control hydraulic cylinder for positioning. CRIO is used to controller and sinus signal generate in FPGA.

This program is used to generate 2 sinus signals to apply hydraulic cylinder for position control of the 2 cylinders (Fs=1000 s=1000). The program works  without any problem for many aspect . But when the program works, if I press stop button it stop some 3-4 seconds later with delay.  Also when it exceeds the test temperature it also stops with that delay. You can see the program structure left side. To access to Realtime and FPGA side DMA method used (Fs=1000 s=1000).  Maximum test frequency is about 2Hz sinus signal.

If someone interest in this problem I can also send the RT dma images. Im waiting for your suggestion to make this program works without any delay. I would greatly appriciate any hints or suggestions about how I should fix this problem.

Note: I attached word document for  info images and expessions

[Ryan-OC]

Hi Sea1,

The delay is likely occuring because of the time it takes for everything to finish in the last cycle or delay over your network. What you could do if you want to immediately stop the process is link all timing loops stop condition terminals to a single stop buttion control on your front panel through a network shared variable. If you need to take into account proceedures that need to occur before stopping I would look into watchdog for deterministic behavior.