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Are two host vi can communicate with FPGA target ?

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Hi

Im using FPGA FlexRio Kintex 7 with 6585B adapter.

i designed a Host panel to download the bitfile to the FLEXRIO , the panel works fine , and the file is download without errors .

Now , im having 2 different Host Vis that i want to run at the same time , to communicate with Target ,

Is it possible ? if Yes how can i implement it ?

 

Thank You.

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You can only load 1 bit file into the FPGA at a time.  So that might be your major issue.

 

Otherwise, sharing resources like this is typically a bad idea unless you put in safe guards to make sure both of your host VIs don't interfere with each other.  Could you share a little more information on exactly what you are trying to accomplish and maybe we can come up with a better idea for you?


GCentral
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Hi ,

There is no problem with only one bit file at a time.

i built two host panels , because there is two much info data , and registers which i want to red and write to the target.

Each panel is full screen , thats the reason why i split them into two vi .

now i want to modify data from one host panel , and see the result that comes from the Target , in another host panel.

 

Thank you in advance.

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Accepted by topic author Cobmetal

Hi Cobmetal,

 

you can have several VIs communicating with your FPGA bitfile!

Just wire the FPGA reference to all of them…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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I have three host Vis (three different files). The first is downloading the bit file , and last two are for Host <--> Target communication.

so at first , i download the bitfile to the FPGA using the first panel and close the panel.

In the other two panels i've wired the FPGA reference .

When Im trying to run the other two panels i've got an error :

NI-RIO:  (Hex 0xFFFF0925) The handle for device communication is invalid or has been closed. Restart the application.

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Hi Cobmetal,

 

then you need to debug your application.

 

It works fine for me:

check.png

Calling 7 subVIs with the same FPGA reference…

Best regards,
GerdW


using LV2016/2019/2021 on Win10/11+cRIO, TestStand2016/2019
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Yeah , you right.

Just see that in of the Vis , there was a reset method.

another question : if i open few FPGA references to few hosts , and i'm configuirng it from bitfile , does the download of the bit files happens from each host ? in what occasions should i check "Run the FPGA VI" , if i open few FPGA references are there any interferences ?

 

Thank You.

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@Cobmetal wrote:

I have three host Vis (three different files). The first is downloading the bit file , and last two are for Host <--> Target communication.

so at first , i download the bitfile to the FPGA using the first panel and close the panel.



There's part of your problem most likely.  If you use a VI to open the reference and then close it, the reference will be discarded with the VI which owns it.  The VI which opens the FPGA Reference needs to stay reserved at least in order for the FPGA Reference not to be destroyed.  Opened references have the same lifetime as the VIs which open them.

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