Any invoke method on host VI stops FPGA VI execution

[solarsd]

Hi,

When the FPGA is running a VI, whenever I call any FPGA invoke method from my host VI (such as "Wait for IRQ") FPGA execution stops. What I am doing wrong?

Thanks,

Lukas

[Danny_Funk]

Lukas,

Including a small example program that shows the behavior your experiencing might be helpful for understanding what is being done incorrectly. If your using the "Wait for IRQ" method there are some caveats that you need to pay attention to. This is noted in the Wait for IRQ help documentation.

Regards,

Danny F

[solarsd]

Hi Danny F,

Thanks for the reply.

While narrowing down the possible causes I've came up with this trivial FPGA analog input VI. The FPGA VI should generate an interrupt when the data is ready, but the Wait for IRQ method always times out in the host VI. I realize that this slightly deviates from the topic, but this issue seems to be at the root of all this.

Why does the host VI always report a timeout even when the wait time is 100x the FPGA loop time?

Regards,

Lukas

[Dave-C]

Hi Lukas,

I haven't been able to recreate a timeout instance using these two VIs, but I'm going to keep trying to with some different configurations.  While I'm working on those however, I wanted to probe for some info.  When the Host VI times out, are you receiving an error message?  If so, what is the associated code and location?  I'm also curious about the wording you've used about the FPGA stopping.  Is it not updating values or does the entire VI go to a 'not running' state and need to be restarted (grid lines on the front panel)?  These answers will give us a better idea of what's going on around this failure and help to troubleshoot it.

Regards,

-Dave C

[solarsd]

Hi Dave,

Thanks for the reply. The error I am getting is 61060 (Message: The wait timed out before the specified interrupt was received; Source: Invoke Method: Wait for interrupt in AI Test Host.vi). But first of all I have something to explain.

I've made quite a mess out of this thread by starting with a "FPGA stopping" issue and quickly deviating from the original topic. I am fairly inexperienced with FPGA programming, so I am picking it up as I go. For the moment I believe we can focus on the "How to use interrupts" issue from my second post. After I've understood this I'll probably be able to solve my initial problem.

Thus my refined questions is: What am I doing wrong in the interrupt-based data retrieval from my second post? All I get are timeouts and the data seems to be garbage too (see picture), I am expecting to see zero volts. The pattern seems to not depend on the sampling rate and the input channel, even when the "channel" is set to Board Temperature. Let me know if I can provide further information.

Thanks,

Lukas

[Dave-C]

Hi Lukas,

The Wait on IRQ help link that Danny posted previously is a pretty good spot to learn about the method.  However, I'm curious why the IRQ method is necessary in this application?  From what I can tell, you're trying to use the interrupt to control the data flow, but I'm just wondering if there's anything about this application specifically calls for using IRQ?  

I'm also curious about which version of LabVIEW FPGA Module you're using and which card are you using?  

Regards,

-Dave C

[solarsd]

Hi Dave, I've read the help entry Danny's link points to. The only thing I'm still curious about is the remark "unless target documentation specifies otherwise" - maybe interrupts aren't supported at all by the FPGA I'm using. The Virtex-II documentation from Xilinx is written at an even higher technical level, besides an "interrupt" keyword search in Virtex user guide turned out empty. I am intending to use interrupts to synchronize host application and FPGA operation, e.g. FPGA would signal the host application when a waveform generation is completed or data is acquired. LabView FPGA module version: 8.5.1 FPGA card installed: NI PCI-7831R (FPGA: Xilinx Virtex-II V1000) Regards, Lukas

[Dave-C]

Hi Lukas,

I've got some other documents I'd like to point you to regarding setting up IRQs.  One relates to the code in the FPGA VI, and the other refers to the Host VI set up.  I think that these steps may help you out in implementing this application and getting past the timeout error.  Let me know if these help and keep us posted on your progress!  

Regards,

-Dave C