LabVIEW
Advice on making my project more efficient
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Hey mrtea,
I had a quick look at your code. But had problems reading it because the VI is so big. Generally, I have the impression that you want to know about the State Machine Architecture. As it looks like you tried to re-create it's functionality (-:
- Using a State Machine (Event Driven) Architecture
- Event Structure
- Find the examples about the State Machine in LabVIEW's Example finder as well! Finding Examples for LabVIEW
- Also, creating SubVIs will be a big benefit for you! Tutorial: SubVIs
In your FPGA code I noticed the StopProgram and StopProgram2 buttons. You could use one button and a Local Variable referencing it instead: Creating Local Variables, Using Local and Global Variables Carefully
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@mrtea wrote:
On a different note, in FPGA world, is the 'wait' function the best way of adding an accurate duration to a pulse. Say if I have a digital pattern of:
H H H L L L (3 high, 3 low)
And for each I extend it by a certain time period using the 'wait' function to make it "stay" at each state for this time period.
Yes. Except you need high-speed execution of a loop that contains non-deterministic nodes as well. Some functions on the FPGA are not deterministic. Luckily, if one doesn't know which one that are, LabVIEW helps. There are several more options than the simple plain wait function:
- Manage Execution Rates with FPGA Timing Functions (FPGA Module) - LabVIEW 2016 FPGA Module Help
- Timed Loops: Page 26 in cRIO dev Guide (a super handy document btw)
- Single-cycle timed loops: Single-Cycle Timed Loop FAQ for the LabVIEW FPGA Module
- How Do I Set the Rate of a Timed Loop on an FPGA Target?
Some of these are based on Clock/Derived Clock you define in/on your cRIO. Also a handy feature.
@mrtea wrote:
I will put a lot of it into subVi s later but just prefer to see everything for now as I am editing and debugging etc.
Well, this is more general advice: Even if you don't believe me now, making your code modular helps you editing and debugging a lot!
By separating the different functionalities of your program into independent modules, you can have a much better overview about the different parts, debug them a lot better, and understand their high-level "cooperation" much easier. Of course this needs you to plan your application's structure a bit, as you need to think about your desired functionality, and then design a subVI for each one. Although this seems like a burden, it helps a lot. As each SubVI has a well defined function and(!) interface, you cannot trick yourself into thinking "it works". But enough of this.
@mrtea wrote:
I have also multiple other signals into the FPGA side. I have all of them in while loops which run in parallel. I did it like this so I can just stop one while loop to stop that signal being sent whilst keeping all other signals being sent. Is there a better way to do this?
I am not sure if I understand this question. The parallel while loops are not in the code you posted, right? If you speak about the FPGA code, then this seems to be a reasonable solution (depending on the exact implementation of course). If I understand it correctly, I'd have one (never-ending) while loop per signal, with a case structure inside, that determines if the signal is active (=outputting a timed signal) or inactive (=outputting a constant 0). As you don't need to worry about CPU usage on your FPGA, you can run it like this. In case you want to be able to gracefully shut down your FPGA application, you need additional code of course.
@mrtea wrote:
I still think the way I am using the pattern functions are wrong however. Will put a simplified version of that for input tomorrow if it is not clear as is.
Looking forward to it!
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Content Cleaner
@mrtea wrote:
I have posted a snippet of my code using the patterns. Ignore the buttons as all they do is exit the code. My question is, if I have my Rio acting under a 40MHz internal clock. I understand this to mean that it is able to sample at a 40MHz rate.
This depends on the I/O channel you are using. Generally, digital IO is fast, analog channels are slower. According to the data sheet the AO can do max. 345k Samples/second accumulated over all channels.
What you also need to take into account is the execution rate of your FPGA code. E.g. having an FPGA I/O node writing to a DO takes 1 clock tick, a normal while loop around it needs 3 clock ticks. That's 4 clock ticks in total, leading to a loop rate of 10MHz. See Why is Our FPGA DAQ Limited to kHz Range when the On-Board Clock is 40 MHz?.
@mrtea wrote:
If I wanted to then plot one cycle of a signal that is (for example) 50Hz. It should have a period of 0.02s. This seems to work ok the way I have plotted it. However, this is not what I get off an oscilloscope when putting it out to the Rio.
Is there something I've done wrong at the very basic level in my code?
So what do you see on your scope? Can you post a screenshot/photo in case it is harder to explain? Looking at your FPGA code, I noticed the "HallEffectTime(uSec)" control which is effectively the loop rate and set to "0". Is this intended? Are you updating it from somewhere? I also noticed that your latest VI generates analog waveforms (like a sine wave), but your inner-most FPGA loop outputs to a digital channel. So your host generates e.g. 0, 0.2, 0.4, 0.6, 0.8, whereas your myRIO outputs 0, 0, 0, 1, 1. Is that intended as well?
I think we should take a step back and rethink your application's architecture. Do your three hall effects always have the same waveform? Is it sine/square/triangle or are that just demo waveforms? Have a look at Waveform Generation with CompactRIO, there are lots of examples in there, it might be very handy for you.
