A true FPGA dynamic reference

[chipper]

background:

I developed a project that is a stand alone ethernet cRIO that has a bunch of logic running on the FPGA. And some PC code that retrieves data from the cRIO (FPGA). I have turned over the PC code to another group to incorporate into their larger project.

problem:

Whenever the PC code runs, because the reference is pointing to an older bitfile, that older bitfile is pushed and runs.  My changes are lost (code is still in flash but my code changes dont affect the data output).

goal:

I want to be able to make changes to the FPGA code, burn these changes to the flash, and when the PC code retrieves the data the changes to the FPGA code is refelcted in the data retrieved. I want the PC code to connect with the cRIO and get the data that it's outputting.

attempts:

I have tried setting the reference to as dynamic, type def, to bitfile, vi, and build spec. I have tried casting using the Dynamic FPGA Interface.vi.  None of these seem to help.

My simulated bench setup:

I have duplicated the issue on the bench with a couple of different bit files. The I/O of both bitfiles are the same. The only difference is the LED flash rate.

It seems whenever the PC connects up to the cRIO which ever bitfile/vi is referenced gets pushed to the cRIO FPGA and thats whats excuted reguardless of whats in the FPGA flash. I can instantly see the flash rate change when the PC code is started meaning the other bitfile is pushed to the FPGA.

Suggestions?

[Jacobson-ni]

I don't know exactly what you are doing but it sounds a bit similar to what is done with the FPGA Advanced Sessions library. Even if it's not exactly what you are looking for it might give some ideas of how to solve your particular problem.

https://forums.ni.com/t5/NI-Labs-Toolkits/LabVIEW-FPGA-Advanced-Session-Resources/ta-p/3500447

[chipper]

I really like what this can do but it's still not what I'm looking for.

The scenario is this:

Monday the PC code is getting data from the cRIO across the network and the parameter "version" returns from the FPGA the value of 1.

Monday night i connect my laptop and push a new version of FPGA code to the internal flash and verify with my laptop the FPGA parameter "version" is now 2 which tells me the new code is on the FPGA.

Tuesday the guys reconnect the cRIO to the network and restart their original PC code and the FPGA parameter "version" is returning a 1.

It seems when they start their PC code the original version (1) was pushed to the FPGA.

I want to modify the PC code so that is connects the cRIO and just pulls the value of "version" without pushing the code to the device.  I thought this was dynamic mode was suppose to do but it doesnt appear to be doing that.

[chipper]

I failed to mention. The code running on the FPGA is monitoring a process. Its starts as soon as the FPGA powers.  The connection from an outside PC is only so the PC and assocated network can monitor parameter values.  But becasue of the nature of the FPGA it can't be interrupted to have code pushed to form the PC on the network.

[Jacobson-ni]

I'm not sure if you are going to be able to do that as when you open an FPGA reference you have to point to a bitfile which will be loaded if it is not already. What you may need to do is have your PCs not talk directly to the FPGA but instead request information from the cRIO which manages the FPGA connection and forwards the information to the requesting computer.

[chipper]

Thanks for the replies. The problem is these devices are NI 9146, ethernet extension modules, no CPU.

I'm running all the data acquistion and logic decisions in the FPGA, no need for a CPU.

I don't think i fully understand what dynamic mode is doing. 

[crossrulz · Accepted solution]

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@chipper wrote:

I don't think i fully understand what dynamic mode is doing. 

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Dynamic Mode is just a way of casting to an FPGA reference into a more generic interface.  This promotes reuse.  Not at all what you are trying to do since you still have to connect via a full bit file.

So since you are just throwing stuff over the wall, you just need to make sure the updated FPGA bit file is thrown over as well.  Your alternative is to go with something like a cRIO-9063 and use the RT portion to act as a communication buffer between the FPGA and a host computer.  I have several systems that are set up this way.  The added benefit with the cRIO is that you can store latest settings as files on the cRIO so the controller can just pick up where it was when it was shut down.

[Intaris]

Show some code, it might be a problem with the "open FPGA Reference" comfiguration.