9203 minimum time change require recompile?

[RVallieu]

If I change the 9203 module minimum time between conversions, do I need to do a recompile on the FPGA code?

When I change the module setting and then open the FPGA it does not indicate that it needs to recompile.

How do I push the change of the interval down?  Recompile the RT Startup Application and deploy it?

[Julianne_K]

Hi RVallieu, 

Basically, if this change affects what is written to your FPGA code, then yes, you need to rebuild and redeploy the FPGA code. However, if the change only affects RT side then you just need to rebuild the RT executable. Hope this helps,