7966R with 5761

[Mac671]

Hello I've looked at:

5761 Single Sample CLIP example.

The exmaple comment states "To allow this example to compile at 250 MHz, the acquisition loop must be pipe lined."

Why is this the fact ? Is this due to the fact that the DDR memory wouldn't keep up with writes if it wasn't pipelined?

What is the reason for pipelining in this case

Thanks,

Maciej

[dan_u]

No, pipelining does not change the rate at which the data is written to the FIFO. It just allows the compiler to read the data and write to the FIFO simultaneously instead of serial execution order. Of course it means that the data written to the FIFO is one cycle delayed, but at these rates that should be acceptable.

There's no DDR memory here.