660x cards

[Ian Jones]

Surely a simple question, I have the 6608 card (which is the same as the
6602 but with a Oven crystal 10MHz clock)

I want to supply a stable clock to other cards in the PXI chassis at
60kHz (not an interger of 10Mhz). How can this be done, and how can it
be proven that the other cards are receiving this clock?

Cheers in advance

[Erin_B.]

Ian,

You have two options here for providing a stable clock source to your PXI devices. First, when you insert the PXI-6608 in Slot 2 of your chassis, it automatically replaces the 10 MHz backplane clock with its 10 MHz OXCO. By doing this, any device in your chassis that is capable of phase-lock-looping to the backplane clock will take on the stable characteristics of the 6608's OCXO. Those devices will also be synchronized to the OCXO. Any clock derived from a timebase (i.e. the 20 MHz timebase on a PXI-6115) synchronized to that OCXO will also be stable and synchronized, so you do not necessarily need to export a clock from the 6608 to the other devices. Devices that support phase-lock-looping to the PXI backplane clock include the PXI-6602, PXI-5112, PXI-6534, and
the PXI-6115. You can look at your devices' UMs to determine if your boards have a PLL circuit onboard.

Your second option is to create a 60 kHz pulse train using one of the 6608's counters and exporting that pulse train over the RTSI bus to your other devices.

Both of these options work equally well for your application. For more information on timing and triggering with the 6608, you can refer to:

http://zone.ni.com/devzone/devzoneweb.nsf/opendoc?openagent&AEFB3825F9A76B838625693800586ACD&cat=51FC6BB34EBE326B862567E500702FAD

Regards,
Erin

[Ian Jones]

Cheers for that, it gives me some hope!

I can't find in the UM if the PXI 6713 is PLL capable, any idea?

Also, the creation of a 60kHz pulse train seems problematic as all I can
see involves divison of the 10MHz clock, and 60kHz isn't an integer.

I understand the idea of using two clocks, but is there any code
examples?

Cheers