5154 digitizer data to fpga

[mstaylor97]

I'm trying to stream data as fast as possible from the the 5154 digitizer to a FlexRIO 7966.  Starting with the  "NISCOPE Fetch Forever" example in LV2012, I can set up the acquisition on the 5154 @ 40MS/sec, 50k chunk of I8 data, and the graph indicator seems to keep up fine indefinitely.

I've tried to then write this data to an FPGA - Host to Target FIFO, and it chokes.  With the FIFO write method inside the 5154 fetch loop, the 5154 eventually errors out due to "overwriting memory" (it's filling up its onboard memory before the HOST is reading it out).   With the FIFO write in a parallel consumer loop (queue driven) the queue just overflows as it can't seem to write the FIFO as quick as the 5154 is providing samples in to the queue.   What am I missing?  The 5154 is using a PCI bus DMA (I believe), so I'd think if it could keep up, the Host to FPGA PCIe bus should be well capable. 

Is there another factor I've not accounted for?   Sorry I can't provide the various VI's since the LV installation is on a non-networked PC.  Any tips or suggestions would be appreciated.

Thanks,

Mark Taylor

[xavvvv]

Hi Mark,

It sounds like you are correctly configuring the Target FIFO side as you are indeed writing to the buffer from the 5154. How are you dealing with pulling your data out of the FIFO? You will need to use a Read Invoke Node on the Host side in order to pull data out of the FIFO appropriately (see this helpful help document). How are you doing this currently? Are you able to retrieve any information on the Host side? 

The Target buffer overflowing sounds like the DMA transfer to the Host isn't happening fast enough. How big are the Target and Host FIFO sizes, and how many elements are you pulling from the Host buffer per read? Here are another couple of tips on Avoiding Buffer Effors in DMA Applications as well as a good introduction on setting up your DMA FIFO. If I haven't touched on any helpful points, getting screenshots of the FIFO setup on both sides of the DMA transfer would help.

Hopefully this helps!

[mstaylor97 · Accepted solution]

For future reference, I ended up resolving this by moving the implementation to the actual FPGA.   I had been running in mode "on development computer with simulated I/O" and no matter what I did with the startup sequencing or FIFO sizing, it just wouldn't work.

After compiling and executing on the FPGA, all is well.  Maybe this is elementary knowledge, in fact I do recall somewhere in my travels reading that timing issues won't be accurately represented when executing in the former fashion, but LV FPGA has sort of painted us in a corner with the simulation/compilation tradeoff.  They didn't include Modelsim, which is the only tool that allows Co-simulation to do functional and timing verification together (we have Questa, unfortunately), and stand-alone VHDL simulation doesn't capture the host interaction accurately (and processor/software timing is impossible to quantify!).  In my situation, the only way to get it to run at speed is in the FPGA, but then I can't see all the things I need to see to debug... ARGH!! 

Any additional links or resources would always be welcomed (on LV FPGA debug and design in general).  I did find a couple things below, which was somewhat helpful:

"The NI LabVIEW High-Performance FPGA Developer's Guide"

http://www.ni.com/tutorial/14600/en/

I found a link to a "FPGA Debug Reference Library": http://www.ni.com/example/31067/en/, but my installation doesn't seem to have this available.

And, looks like 2013 may be adding some functionality to help alleviate some of this via the Desktop Execution Node mentioned here at "Testing and Debugging LabVIEW FPGA Code"

http://www.ni.com/tutorial/51862/en/