100us delay for DAQ!

[graduate student 44]

i'm running a 120mhz counter in the fpga vi. i'm also having several DAQ card running on the same chassis. i routed the "AI Convert" signal of the master card to a RTSI bus line. so each time a data sample is taken, the fpga card is triggered. i take a timestamp every 32000 samples, which is also the sampling rate. but somehow the Tn+1 and Tn i got is not exactly 1 second apart: Tn+1 - Tn = 120000957, not 120000000. i cannot figure out what's going out. i believe the struture of the code should give me an exact 1 s. i'm attaching the fpga vi.

[Kevin_Price]

I've got a couple ideas, but take them with a grain of salt -- I haven't used the FPGA card and don't (yet) have LV 7.1 to look at the code.

First of all, have you verified that when you set up your AI card for 32 kHz sampling, your actual sampling rate is indeed 32.0000000 kHz? I suspect the answer will be yes because 32 kHz corresponds to exactly 625 cycles of the 20 MHz clock on the E-series boards. In general though, this quantization error is something to watch out for.

More likely, you're simply dealing with a discrepancy in the accuracy of the two cards' clocks. A quick look at specs on some E-series boards shows an accuracy spec of only about 0.01% where you're finding a discrepancy of less than 0.001%.

Can you generat
e an output from the FPGA card to drive your AI card? For example, if you were able to toggle a DIO on the FPGA every 1875 cycles of your 120 MHz counter, you'd produce a 32 kHz clock. If you set up your AI to use that clock for sampling, you should get "exactly" 120000000 counts per 32000 samples, give or take signal propagation variations.

Note: the above is based on interpreting your description to mean that your AI card is only sampling a single channel, since you seemed to equate the sampling rate with the "AI Convert" rate. Either that or you've got a S-series board that does simultaneous sampling.
If you are sampling several channels on a multiplexing AI board, you may need to generate both a scan and channel clock (a.k.a. sample and convert clock under DAQmx) with the FPGA.

-Kevin P.

[Christian_L]

Unfortunately Kevin didn't know that you are using a 4472, but his answer is pretty much correct. The actual sample rate on the 4472 will not be exactly 32,000 Hz due to the circuitry on the card. The specs for the card state that the sample frequency is set in increments of 95.37 us in the range your are sampling. You can get the actual sample rate used by the card as one of the outputs of the AI Start VI in LabVIEW. Please check what the actual sample rate is and if it corresponds to your measured sample period.

In addition the frequency accuracy for the 4472 is 25 ppm and your measured sample period is within 8 ppm (~1 part per 120000) of your expected result.

Christian L

[graduate student 44]

hi Kevin. i'm using pxi-4472. first i double checked that the actual sampling rate is 32000.000000. i also realized that for 32000 data samples, "AI convert" triggers more than 32000 times!?!

after some more research, i realized that "AI scan start" or "Scanclk" might be the actual signal i want. i've been trying to route either one of them to an RTSI line, but labview doesn't seem to allow it.

for a 32k sampling rate, i want a 32k signal, each triggered by a data sample being taken. could you confirm that either "AI scan start" or "Scanclk" is the right signal? and how do i route them to be readable from an fpga vi?

the master card is in slot 2 and i've set all triggers to "trigger right".

thanks!

[graduate student 44]

thanks Christian. you are awesome. so finally i'm turning back to "AI Scan start" and "Scanclk". one of them seems to be right signal, with each trigger corresponding to a data sample being taken. see above comments i wrote for Kevin. I've looked through manuals of 4472 and 1006, but couldn't found anything about these signals, not mentioning how to route them!