Hi Folks,
I'm trying to find out how to simulate an FPGA subVI on my desktop so that (a) I can call my unit test automatically and (b) not modify the code under test for the purposes of functional validation ((I'm happy to build a testbench around it). It would seem that the desktop execution node should do this, but I face problems with code that has internal feedback registers. Specifically, I would like to input an array that represents the vector's input cycle by cycle and then analyze an output waveform.
I've included a screencap of the manual way I do it now, basically by adding a while loop around my code, and putting a breakpoint after each iteration, and then adjusting the front panel controls. One might think of ModelSim by Mentor Grapics as to what I'm trying to achieve, but in a very basic way, such that I could say run the code from the Unit Test Framework.
Just to clarify, this is where I would like to end up if I test the simple latch as above, but I keep getting error -61449