with NI FPGA Timekeeper it is much easier. You could read time in nano-second resolution any time and then you could timestamp each sample when you want.
Did you download NI FPGA Timekeeper?
When yes then
Thanks a lot for your input.
You mean after using this FPGA timekeeper I would no longer need the 'User controlled I/O sampling VI' which I used for data acquisition . But the NI 9223 samples at 1 MS/sec if used with the 'User controlled I/O Sampling' otherwise it samples at a much lower rate.If I use a sequence structure and make the NI 9223 to acquire and in my other frame of the Sequence Structure if I use 'FPGA Timekeeper.lvlib:Get Time.vi' to obtain timestamp of the acquired sample then the timestamps would be acquired at a much lower rate and not in MS/sec duration.
I can neither create a subVI for my acquisition VI because it has user controlled parameters like 'Number of samples' which need to be acquired from the user at the time of running the VI and hence, has to be the part of the topmost VI .
Due to these issues I am unable to link the acquisition VI with the timekeeper one.I have checked the 'Acquisition using Metronome VI' but I am not quite sure if acquiring signal using NI 9223 in the same manner could it allow me to sample at 1 MS/sec.
If I do not apply the 'User Controlled I/O sampling' . The NI 9223 samples at 350 KS/sec. Hence, it would be not possible to timestamp the signal at microseconds interval. In order to timestamp at microseconds I need to use the 'User Controlled I/O sampling'. I am not sure how to use the 'NI FPGA Timekeeper' VI to carry out the timestamping in microseconds because of these constraints this seems to create challenges in the implementation. Can you please help me better understand this issue ?
I will try the implementation you suggested ,if possible could you please post the snapshot of the code/VI you just suggested that would make it much easier to understand.
I have got two specific questions about the VI
1:How to access the Get Time VI , get conflict issues.
2hould the 'Synchronize to GPS:cRIO' VI be placed on the host (i.e.cRIO) because the acquisition is on the FPGA VI and should any open reference VI should be provided to link this host VI to the acquisition VI running on the FPGA or should this main host VI be run independent of the FPGA VI.
I am acquiring data at the rate of 1MS/sec using NI 9223 and cRIO 9030 controller . I use DMA FIFO for data acquisition . The architecture used is the 'User Controlled I/O Sampling' as mentioned in the Labview 2014 examples section.
I want to timestamp at microseconds resolution using NI 9467 . Is it possible to integrate the acquisition VI with the 'NI Time Sync FPGA timekeeper VI'.Ihave this specific question because I am really new to Labview FPGA and none of the posts in the discussion forum seems to highlight this approach.
I need an urgent help and would be grateful if anybody could help.
Please find attached the snapshot of the code I tried yesterday.
Could any one please guide me with the interfacing of FPGA timekeeper with the NI Time Sync FPGA timekeeper.
Please note the second snapshot is not updated . I have used two DMA writes the first corresponding to the acquired sample value and the second corresponding to the output of the Get Time. VI from the NI Time Sync FPGA Timekeeper.I need an urgent help as this kind of interfacing does not work in my case
sorry I am on annual leave.
I think you should read time when Pulse for AI was generated. Your implementation will read time when you read values from module. Not time when pulse/trigger for AD convertor was generated. My implementation is not ideal, because module still need some time to acquire data.
GPS timestamp is FIFOed on FPGA from pulse generate loop to FIFO loop. Here is configuration:
I am using one DMA FIFO for AI values (24 bits) and GPS timestamp (64 bits = U64). U64 is spitted to 2x 24 bits and 1x 16 bits. Then 'type casted' to same type as AI values (+/-24,5) and sent by DMA Fifo. On RT site you have to convert first 3 FXP numbers back to U64 GPS timestamp and rest is yours AIs.
I didn't try to compile it, but is sould be ok.
Thanks a lot for your input
I will definetly try this . I just had one more question . Could you please suggest an approach by which I would seperate the timestamp and the sample values on the host. Since , I want to log data continously for long period.
In this case should I log data on the cRIO or should data be logged onto the host(PC) using network streaming.
I tried running the VI on the FPGA and was able to compile it However, I am not able to verify the working unless I make changes to the host VI.
I plan to make changes to the host VI in order to seperate the sample value and its corresponding timestamp. In the FPGA since two FIFOs are used one corresponding to the sample and the other corresponding to the timestamp. Hence, could you please suggest if I need to use Interleaving on the host side in order to obtain the timestamp values which were divided into two 24 bit values and one 16 bit value and later use Interpolate Array for bundling them and later convert it into unsigned 64 bit. and on the other end obtain the sample values from the second FIFO and later use functions on the waveform palette to plot the values of timestamp (in microseconds)versus the sample values.
I wish to communicate from my FPGA target to the host (PC)over an ethernet so what would be the best way to implement , taking into consideration that datalogging is to be carried out for longer time.
I would be grateful if you could also help me deal with the VI on the host.
Thanks once again .