Inverse and pseudo inverse Matrix on FPGA

[togoto]

Hello everyone,

How can I calculate inverse/pinv matrix on clock driven logic (*.gcdl), for FPGA? (Labview Comms 2.0)
May be anybody has solution for this task? Or what the best algorithm i can use for this task?

Thank you.

[Danny_Kaps · Accepted solution]

Hello togoto, 

We do have Inverse Matrix and Pseudoinverse Matrix VIs for host-side code, but these are not supported on FPGA. The reason for this is because without a known matrix size, there is not a way to implement a dynamic matrix math function (the compiler could not know how many resources that would require). When considering that most inverse matrix algorithms hinge on division, which is very resource intensive on FPGA, that provides another reason why we wouldn't be able to implement it in CDL.

That being said, Comms does have Matrix Multiply and Matrix Transpose functionality that you can implement in CDL. As long the matrices are always of a fixed, consistent size, you can implement a custom algorithm to accomplish matrix inversion and pseudoinversion. It would require careful pipelining to ensure it worked in a single clock cycle.  

Could you elaborate on what exactly the application is meant to accomplish? If possible, moving matrix math to your host-side VIs might be the best approach.

Best,

Daniel

[togoto]

hello Daniel,

I'm trying use inverse matrix for Zero Forcing on receive side, and can't move calculation to host-side. I have fixed size matrix. We compile file for FPGA and calculate the needed resources, isn't it?

Danial can you give some links or material to read about algoritms with Matrix Multiply and Matrix Transpose which i can used for create inverse matrix on fpga? Can you advise me the most simple algorithm for this?

I would be grateful for any help

[Danny_Kaps]

Hello togoto,

I have been looking around, and it looks like this is actually a really interesting problem that people have been trying to solve for quite some time. The major issue is that matrix inversion and pseudo-inversion is, by its nature, not a hardware-friendly activity.  Doing this in a single clock cycle presents a significant additional challenge, and would probably introduce large amounts of latency.  I found this research paper dedicated to proposing a potential solution:

https://www.researchgate.net/publication/224310123_FPGA_design_and_implementation_of_Direct_Matrix_I...

And this Xilinx forum post where users were discussing this problem:

https://forums.xilinx.com/t5/DSP-and-Video/Need-ideas-for-the-design-of-a-matrix-pseudo-inverse-bloc...

According to one poster, "The problem you are trying to solve is an active research issue in the FPGA design field. Accelerating the pseudoinverse computation of matrixes by hardware is a very complex and challenging task." You may want to try branching out to other forums of FPGA design engineers or research communities to see what other proposed solutions exist. Post back here with anything you find! I'm sure many of our users (myself included) would find approaches to this challenge equally interesting!

Best,

Daniel

[togoto]

Thank you very much Daniel,

I will necessarily read these articles. Now i'm trying make QR algorithm. Inverse triangular matrix is more simple, and i hope it possible make on FPGA.