ERROR library path

[Leonardo_Castillo]

Hi all, I'm working with a USRP NI 2942R and my question is related to use my hardware.

I need of basic hardware getstarted because, when I make new development and use DDC an DUC block. It not work. the Error is a path of library IP*** and VHL file.

Thanks in advance.

[Ben_Co]

Hi Leonardo,

Thanks for posting to the LabVIEW Communications forum! What code are you running that's getting you this error? Could you post it here? It sounds like the VI is not pointing to the correct path, or there was an error in installation. 

Also, have you tried opening one of the starter examples under "Examples" » "Hardware Input" » "NI USRP Host"? Alternatively, if you plan on doing FPGA programming, I'd recommend one of the starter projects, under "New" »  "PC USRP RIO 40 MHz Bw Single-Device Streaming". 

Thanks,

BeenCoughin

[Leonardo_Castillo]

Hi BeenCoughin

I do FPGA programming.

when I started a new "PC USRP RIO 40 MHz Bw Single-Device Streaming". the project  to create so much files  and I want to select only the minimum.

these are the listings that collects>

for Host
Open Device
Close Device
Configure Signal (Level)
Configure Signal Common
Configure Frequency
Configure Frequency Shift
Calculate Sample Rate
Configure Signal Level
Configure RF
Configure Stream
Configure Start Trigger
Configure Time (Single)
Construct Channel
Write
Write Tx Data (I16)
Write Tx Data (U32)

for FPGA

DDC Multi channel
DDC Single channel
DUC Multi channel
DUC Single channel
Imput stream control
Output stream control
Register
Start Trigger
Start Trigger Time
Read FIFO Multi channel
Write FIFO Multi channel
6-1 mux
FDPB1spc2x1pPL.eip
FDPB1spc2x2pbPL.eip

But here problem, need files into de folder VHDL that path is fail..

I understand your suggestion.  Actually, I use "new" "PC USRP RIO 40 MHz Bw Single-Device Streaming".

Where I find more information of how use  FPGA programming?

I use Learn, Examples and on-line manual. but I was not entirely clear how is communication of FIFO "Host-to target" "target-to host" .

Thank you again

Leo

[Ben_Co]

Hi Leo,

Those are definitely good getting started resources. With regards to Host-to-Target and Target-to-Host FIFO's, they are data transfer structures that pass elements on a First In, First Out basis. A Host-to-Target FIFO, for example, would stream data from the host down to the target. I believe that this would be a good document to read over for a lengthy explanation of FIFO's: http://zone.ni.com/reference/en-XX/help/371599H-01/lvfpgaconcepts/fpga_transfer_data/

Additionally, there is an example in LabVIEW Communications called "FIFO" under "Examples" » "Programming FPGAs" » "Clock-Driven Logic", and this may shed some light on their functionality. 

If you have other specific questions regarding the streaming project, let us know! 

BeenCoughin