04-11-2008 07:32 AM
04-14-2008 06:54 AM
Hi,
Yes it's possible to implement this into FPGA, if you adapt the electrical signal.
You can found on the link below all information about this :
http://digital.ni.com/public.nsf/allkb/7ADB475DF68DAB518625713A0052799A?OpenDocument
Regards,
Christophe S.
Account Manager East of France І Certified LabVIEW Associate Developer І National Instruments France
04-14-2008 07:41 AM
05-15-2008 01:09 AM
Yes it is definately possible. We did this recently on a project (same 8 Mbit/s) using the 9401 module. For 422, I would use a PXI-78xx series, then use the GeoTest http://pxi4test.com/downloads/pdf/GX5641DS.pdf GX6541 board to easily translate the IO to 422. Their board handles up to 35 MHz.
I also tested B&B Electronics 422-to-TTL converter http://www.bb-elec.com/bb-elec/literature/422TTL_4305ds.pdf and it didn't do too bad at 10 MHz but had about a 16ns of rise time when I used a 9401 (which has a about a 10 ns rise time).
05-15-2008 01:10 AM - edited 05-15-2008 01:14 AM
Also for the code we just started with the 232 example but then modified with to use a SCL where we could precisely control the rate and delays on the data lines.
05-20-2009 08:37 AM
Sorry JoJi1 for reopen this old thread.
I need to implement a custom communication protocol with cRIO with 9401 at 2 Mbps with the output at the electrical level of rs422.
Could you confirm me that there are no problem using the B&B Electronics 422-to-TTL converter?
Thank you,
Giulio Quadrini
05-31-2009 11:44 PM
Hi Dongiulio,
Yes, the B&B converter worked well past 2Mbps. I don't have the scope results of my findings, but I tested it up to 10MHz and it was fine for our purposes of less than 10% rise time.