9870 individual buffer for each port

[j3r3mi]

Hi all, i search all examples and this forum, i found nice app for NI 9870. However what u needed wasn't available. Most of the examples either uses one port or sharing one FIFO (Cont Read / On Demand Write) for all 4 ports.

I need a FIFO buffer for each port, so i can have some check number of bytes for each port and read the number bytes at each port.

In summary, the FPGA VI would continuously read from each port and add into its own FIFO buffer.

I have top level Sub-VIs encapsulates the R/W operation.Similar to VISA's VIs for serial.

I'm using 9012 and 9074, which i tired and i can't have more than 2 DMA FIFO/ 😞

Anyone can kindly help me out??

MANY THANKS!!

[KateB]

Each cRIO can have only 3 FIFOs.

You must find a way to count the Byte on real-time controller.

[j3r3mi]

Thans for the reply

[j3r3mi]

I have another question. If i'm using the hybrid mode. I'm only left with one FIFO. If i intend to use this FIFO for my 9870, how can i use this FIFO for bi-direction?

There's only 2 types of FIFO, "Target to Host" or "Host to Target".