RRC filter generated to FPGA code, and results is different

[GSAO]

Hi,

I need a RRC filter to pulse shape my digital input before going to modulation.

Firstly, I used the "DFD Raised Cosine Design.vi" to filter in my computer, the result is very good.

Secondly, I place the "DFD Raised Cosine Design.vi" to the "Generate LabVIEW FPGA Code" to converter the filter that can be use in FPGA.

Lastly, I tested the generated FPGA filter, the result is different from the result in the computer.

I attached all the printscreen and vi of my RRC.

Can anyone help me on this issues or any solution for RRC using in FPGA?
Thank you.

Regards,

Eton