NI 5640R Help file Correction: Host-FPGA Communication Errors

[JerryAL]

The help file is incorrect on the following section.  It will be updated to something similar to the following.

NI 5640R Help / NI 5640R Programming / Tips and Troubleshooting / Host-FPGA Communication Errors

I get a pop-up indicating that an error was detected in the communication between the host computer and the FPGA target.
 

Error -61046 (above) may occur when trying to read or write controls or indicators that are in a slow clock domain. For example, you may see this error if you have a control/indicator inside a single-cycle timed loop that is clocked by the ADC_0_Port_A_Clk and have configured the ADC 0 to decimate by a large value (larger than 128). Such a setup can cause this problem because the control or indicator is being updated very slowly, and the communication times out while trying to access it. Such a configuration is shown below.

To solve this problem, the control or indicator must be located in a clock domain that is faster (like the default Top-Level Clock). You can then use local variables to transfer the value to a slower clock domain, as shown below.  When moving a control to the Top-Level Clock domain, change the control to an indicator.  The Read/Write Control in the host VI will continue to be able to the dedicated resources on the FPGA which represents this indicator.

Message Edited by Jerry_L on 06-20-2006 02:16 PM