multirate sampling using CLK IN with PXIe-5922

[Garcas]

Hi

I am working in an application where I need to change the sampling rate of an acquisition between 500 ks and 5 Ms without stopping the acquisition. The idea is to be acquiring continuously and be able to change the sampling frequency live depending on external events

I was thinking about doing this using a PXIe-5922 and controlling its sampling frequency using the external sample clock input (maybe I would have to change the decimation factor by software as well?) connected to a signal generator (5404?) or some other clock generator whose frequency I can change without stopping the signal (maybe some specific development on PXI-7833R). My concerns are:

• Reading the 5922 spes I am not sure if I can change its sampling frequency between those values (500 kHz and 5 Mhz) using the external sample clock input without stopping the acquisition (my experience with other DAQ is that when you have to do any programming of the instrument the acquisition stops during the programming phase)
• If the above can be done, I guess my second problem will be to determine in the acquired data where a change of the sampling frequency has happened (as the driver will not know if I am using an external clock)… but I am not yet much worried because of this J

I have not buy the hardware yet until I am sure I am in the right way... so any help will be much appreciated

Best regards

Guillermo

[Cristobal]

Hello,

according to the help, you are able to use frequency ranges between 500K and 5M ( NI High-Speed Digitizers Help - Devices - NI 5922 Overview - Clocking )

Reference Clock

The reference clock is used in the NI PXI-5922 PLL circuit to synchronize the sample clock to the reference clock. The NI PXI-5922 can accept a reference clock from its front panel (CLK IN) and from PXI_CLK10. This reference clock can be any frequency from 1 MHz to 20 MHz (in 1 MHz increments) if it is provided to CLK IN. The PXI_CLK10 is always a 10 MHz clock. The frequency stability of the sample clock matches that of the PLL reference clock when the two are phase locked. In turn, phase locking synchronizes clocks of multiple devices that are phase locked to the same reference clock. The default setting for the NI PXI-5922 reference clock is None, or not to use a reference clock.

When an acquisition is in progress you can't change the sampling rate using a VI or property node, but using an external clock connected to CLK IN input you will be able to change the rate of that signal and the 5922 acquisition rate will change accordingly.

But I think you will not be able to detect that rate change by software or programmatically because the driver will not know which is the output frequency.

I hope this helps.

Regards

crisR

[Jeff_B.]

Guillermo,

Keep in mind the Reference Clock is used to generate the internal Sample Clock.  Changing the frequency of the Reference Clock will result in the same Sample Clock frequency.  Also, changing the Reference Clock frequency should not be done while acquiring since the device's clock circuitry needs to be configured based on the Reference Clock frequency.  I don't think this solution will produce desirable results for these reasons.  Unfortunately, the 5922 does not accept an external Sample clock from the Clock In terminal since the Sample Clock needs to be extremely high quality to meet the device's specifications.

Do you really need to run continuously across different sampling rates, or could you afford a small amount of reconfiguration time between frequencies?  If you can, then you can also avoid the additional complication of not knowing where in your acquisition the sampling rate changed.  Could your application run continuously, then reconfigure the sampling rate when a trigger is received?

[Garcas]

Hi Jeff,

Thanks for the info, but , wow, those are really bad news for me! I was very happy because I thought I could do it with a 5922, but it seems it's not going to work. I even had found allready a solution to overcome the problem of knowing when the sampling frequency (Fs) would change 😞

The thing is that I do need to be able to change Fs it without loosing information during the process. What would mean "small amount of reconfiguration time"? In my application the total acquisition time is around 60 seconds, and I will be acquiring at Mhz, so a "small amount of time" can mean a lot of information (relative to the acquisition duration).

I have allready developed a similar application for "low frequency" signals (kHz) based on DAQ cards using the external clock input, but now I need to go up to MHz, so I was looking for the appropiate hardware. I need 12 bits minimum resolution and the highest possible data transfer bandwidth so that's why I chose PXIe... but if I cannot use the 5922, I don't see many options 😞

Guillermo

[Jeff_B.]

Guillermo,

Note, we currently offer the 5922 in PXI and PCI only.  However, the PXIe-5122 (100MS/s 14-bit) might be worth considering for your application.  This device can also accept an external sample clock through its clock in connector.    Please note though, the 5122’s minimum external clock frequency is 30MHz, so if an external sample clock is required for your application, you will need to set a decimation rate through SW in order to achieve the 5MS/s rate.  I do not recommend changing the clock rate during an acquisition on any of NI’s high speed digitizers since this could result in clocking errors returned from the driver.

One alternative you have with the PXIe-5122 is the ability to acquire over your entire 60s time interval at 5MS/s and stream that data to the host through the express interface for further analysis.  In fact, you could probably get away with streaming the 5MS/s waveform in PXI since rates up to 100MB/s are achievable, but will be system dependant.

Hope this helps.

[Garcas]

I love computers... I was talking about the 5122 since the begining, sorry I should not wear my boxing gloves while typing 😮

yes, I saw in the specs that I might need to set the decimation rate through sw, but I wonder if it will stop the acquisition (?). But what really concerns me is your suggestion about the driver erros that could be produced... would it be possible for somebody at NI's to test this? I have talked to NI's people here in Spain to do this test but they cannot do it because they don't have any PXIe-5122 😞

I have also thought about the other possiblity you suggest, streaming to the host and change the sampling rate by software. It would allways be possible, but we are really interested in the other possiblity. This is part of a research project on DAQ systems, where we are trying to demostrate the advantadges that hardware multi rate DAQ can have in many applications. The idea is to have intelligent DAQ systems that can monitor the signal being acquired to decide the optimum Fs needed during the acquisition, and even being able to adapt it live. As I mentioned earlier, we have allready a system working for low frequency signals (kHz) so we would like to try to do something similar for higher frequencies

thanks again

PS. I promise to through away my boxing gloves 😉

[Jeff_B.]

Guillermo,

I think an S Series Multifunction DAQ device like the PXI-6115 might be better suited for your application.  This device should allow you to change the external sample clock rate during the acquisition and offers 12 bits of resolution @ 10MS/s.  Also, as I mentioned before, the PCI bus should be able to keep up with these data transfer rates assuming it is not being heavily loaded by other devices in the system.

The 5404 seems to be a good choice for your clock source.

Good Luck.