sbRIO-9651 Max DIO Speed?

[markgtr813]

What kinds of digital input and output speeds are achievable on the 9651 SOM? I have an application that currently uses a sbRIO 9606 with external serdes because of the 9606's limited I/O speeds. I am wondering if I can get away without a serdes or pull the serdes into the Zynq on the 9651.

Thanks,

Mark

[jspinozzi]

We have 1 and 2 MBPS working on the 9606 and although I can't announce success until I have data to prove it, we're working on some faster speeds, as well as some MUCH faster speeds on RIO SOM.  We will be doing some real testing in the next few weeks, and we do these kinds of products and services (COTS boards as well as custom boards).  If you're interested, let's get in touch and discuss pricing and specs.  Or if you're just interested in hearing if we got it working, we can copy you on our announcement(s) and data when they're confirmed and go public.  But suffice it to say it's possible to go those speeds above, and still faster, integrated directly into the mainboard.  Call if you like +1-619-988-4596 joe.spinozzi@cyth.com

[Kevin_Hooper]

I do not see standard FPGA digital input/output reaching the speeds of an external serdes.

On the 9651, I have run confidence tests with digital outputs looped back to digital inputs.

I stopped when these confidence tests passed at 75MHz (scope showed good waveforms

at each input used and there was no bad data in a 4 hour soak test). I believe maximum

speed depends on the signal termination and selected drive level. My tests used 3.3V
LVCMOS with fast slew rate outputs.

My 9651 application streams 35MHz 6 bit data through an interleaved signal/ground ribbon

cable with no data corruption.

[tannerite]

Based on what we have tested, our guidelines are 80 MHz for single-ended I/O and 200 MHz for differential I/O. We have not intentially pushed the limits of these as there are many variables that can impact this specification from board level effects and Zynq capabilities. The slew and drive strength mainly impact signal integrity, not speed. It is possible that you can achieve speeds beyond our guidelines, however. The limits stem from the capabilities of Zynq -- whatever Zynq can achieve, the SOM will most likely achieve.

For example, the GMII interface on the secondary Ethernet port on the SOM is running at 125 MHz, single-ended and is source synchronous. This meets timing but this is of course dependent on how loose or tight your timing requirements are with the device you are communicating with.

Kevin, I am glad to hear that you were successful at 75 MHz through a loopback.

As for the external versus internal SERDES question, this depends on your I/O speed. If you are approaching the aforementioned maximum guidelines and can not compile the design, you may want to continue using an external SERDES. If you are below the guidelines, you can instantiate ISERDES2 or OSERDES2 Xilinx primitives within the Socketed CLIP.

One important thing to note here is that it is highly advisable to timing constrain your I/O (Data, Clock) by adding constraints to the Xilinx XDC constraints file that gets generated as part of the Socketed CLIP; otherwise, your data and clock skew may not be what you are expecting or require. NI does not constrain the timing on the I/O and it is up to you to implement the timing constraints within the XDC file.

- Tanner

[Mrmas]

Hi,

I have been looking at the NI 9651 for an embedded application which requieres some high speed analog inputs. I have been looking at various ADC and it seems the most common methode is a serialized digital output to save io lines.

The analog input speed we need is 20 Msps and 12 bit resolution, which would mean io lines needs to read data out with a rate of 240 Mhz (serialized) to have continous sampling. Is this not achivable with the sbRIO-9651 or am i misunderstanding something about the process?

I was looking at using SPI interface for this, but mabye there is another more efficient technique? Preferably something which there is sample code available for

Thanks

[MrJackHamilton]

Mrmas,

The serialized interface I2C/I2S has limited speed. You'd need to goto a parallel data path to the SOM, this would be something like 16 to 32 I/O lines to the SOM. This would give you the maximum bandwidth to stream data into the FPGA.

We are looking to do this on one of our projects. We are currently working on an I2S interface for a 60kHz ADC..at 60KHz, I2S is fine.

Regards

Jack Hamilton

[Mrmas]

I see. Thank you Jack, I will look more into parallel ADCs.

Good luck with your projects.

Regards

Mas

[kalyanramuv]

Hi Mark,

As Tanner pointed we were able to VHDL Code synthesized for speeds greater than 200MHz in our R&D for a project using differential I/O. If your application can leverage DDR inside the FPGA, you can practically double the data rate (2x 200MHz = 400MHz).

I am interested in knowing more about your application needs. We do have another product in pipeline which might fit your application better. Feel free to send me an email if you want to discuss about this further.

- Kalyan

[kalyanramuv]

You can tranfer data from 20MHz, 12-bit ADC using serial interface. However, as Jack mentioned SPI/ I2C might not provide you the data rates you are looking. In addition, you have to take advantage of serializer/ deserializer (SERDES) blocks on FPGA to transfer data at those rates. SERDES on FPGA takes serial stream and converts it into parallel data inside FPGA.

Using SERDES requires little bit of advanced FPGA knowledge. As I mentioned in my previous post, if the ADC chip supports DDR, you can achieve even faster rates.

I believe the CLIP for FlexRIO Module digital modules such as NI 6585 demonstrates usage of SERDES.

- Kalyan

[Mrmas]

Hi Kalyan,

It seems i have much to learn.

When you say use SERDES blocks on fpga you mean taking input from the ADC chip in serial form and converting it to parallele inside the fpga to work with? Wont the Di line used for the serial input need to be >200 Mhz to get all the input still? I guess it might be easier to achieve those rates if the data is worked with in parallel when it gets in.

I was also wondering about the DDR solution. This is something i have seen some ADC chips support, but i was never sure how that would be used in the ni 9651. Is there specific io lines which support ddr or is it a specific way to read the data from the lines(i assume this is what is correct)? If so is there sample code with labview fpga for reading serial input with DDR?

I am asking lots of questions here, mabye there is some manual or white paper you could recommend me so i can find some answers by myself too?

Last, is this an example of SERDES or is it something that comes with the fpga module?

https://decibel.ni.com/content/docs/DOC-24412

Regards

Mas