Hardware PTP (IEEE 1588) for sbRIO 9651 SOM FPGA

[AndreasStark]

Is there a way to discipline the 9561's FPGA oscillator and phase-lock loop it to precision time protocol or 802.1AS TSN.

Goal is to have

1. hardware PTP to have better accuracy
2. not needing the FPGA timekeeper to prevent FPGA based data acquisition from drifting away from network time

We're designing our own carrier board, so any hardware changes/requirements would not limit us.

Thanks for your thoughts

Andreas Stark

[nanocyte]

What's the network time clock frequency? I'm wondering if you can implement a PPL in the FPGA fabric. I'm also interested in external clock sync so if someone knows the answer to that, I'd be interested.

[AndreasStark]

I'm looking for a way to implement time based synchronization (PTP/TSN), not signal based (PPS, ....), so PPL does not help.
More specifically my questions are:

- is there a way to use the 9651's primary or secondary NIC for hardware timestamping of ethernet packets (needed for high accuracy clock sync)

- is there a way to discipline the FPGA oscillator, maybe by using some 3rd party CLIP or VHDL modifications

I'm after doing the same that the TSN cRIOs are doing, High Level Overview of Time Synchronization in NI-TSN products - NI Community -> slides 5,7

Thanks in advance

[NikitaProrekhin]

Hi Andreas,

I have the same questions. I hope someone from NI will answer it 🙂

[resono-mp3]

same question - hello NI?

[Nathan_R]

There is not a supported way to do this with the 9651 SOM. This is supported, just like cRIO, on the latest generation of sbRIO products. 

[AndreasStark]

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@Nathan_R wrote:

There is not a supported way to do this with the 9651 SOM. This is supported, just like cRIO, on the latest generation of sbRIO products. 

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I'd love to buy 100 latest gen 9651 successors right away 😉

I'd be fine with an unsupported way, too. I would appreciate any hints in what direction to look, I assume there is at minimum some kernel switches+rebuild, maybe some additional vhd necessary to unlock hw time-stamping. Is there any way at all to discipline the FPGA clock on the 9651?

Other than that I came across the FPGA timekeeper IP which works for my use case: I want to drive a 1MHz clock to an ADC for fast sampling. The MHz clock should be phase locked to ptp. But I'm open for better suggestions.

Thanks in advance