FPGA Gated Counter

[Smootastic]

Overview

This example shows how an FPGA gated counter subVI can be used for calculating latency and throughput of the High Throughput Square Root function.

Introduction

The FPGA gated counter subVI can be used for a variety of applications, such as memory addressing, timing control and event counting. This subVI has a gate input, to integrate with high-throughput FPGA designs.  The subVI is also polymorphic, allowing smaller count values to preserve resources, if necessary (up to 32-bit values).  The counter mode can be switched to 0-indexed so can be wired directly to a memory method.

The example below demonstates how the FPGA gated counter subVI can be used for calculating the latency and the throughput of High Throughput Square Root function.

Steps to Implement or Execute Code

1. Open FPGA-counter.lvproj

2. Add your FPGA target and move all the FPGA items from the existing FPGA target to your target

3. Compile fpga-counter.vi

Requirements

Software

LabVIEW FPGA 2009 or newer

Hardware

Any NI FGPA target

Additional Notes

For an example of using this VI, refer to NI Developer Zone Community: FPGA Serializer/Deserializer.

**This document has been updated to meet the current required format for the NI Code Exchange. For more details visit this discussion thread**